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-rw-r--r--src/mem/cache/base.hh3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/mem/cache/base.hh b/src/mem/cache/base.hh
index bda3df34a..cd2f55246 100644
--- a/src/mem/cache/base.hh
+++ b/src/mem/cache/base.hh
@@ -129,7 +129,8 @@ class BaseCache : public MemObject
*/
void requestBus(RequestCause cause, Tick time)
{
- DPRINTF(CachePort, "Asserting bus request for cause %d\n", cause);
+ DPRINTF(CachePort, "Scheduling request at %llu due to %d\n",
+ time, cause);
reqQueue.schedSendEvent(time);
}