diff options
Diffstat (limited to 'src/mem/cache/base_cache.cc')
| -rw-r--r-- | src/mem/cache/base_cache.cc | 17 |
1 files changed, 15 insertions, 2 deletions
diff --git a/src/mem/cache/base_cache.cc b/src/mem/cache/base_cache.cc index be9769fdc..451da28e8 100644 --- a/src/mem/cache/base_cache.cc +++ b/src/mem/cache/base_cache.cc @@ -117,11 +117,24 @@ BaseCache::CacheEvent::process() if (!pkt) { if (!cachePort->isCpuSide) + { pkt = cachePort->cache->getPacket(); + bool success = cachePort->sendTiming(pkt); + DPRINTF(Cache, "Address %x was %s in sending the timing request\n", + pkt->getAddr(), success ? "succesful" : "unsuccesful"); + cachePort->cache->sendResult(pkt, success); + if (success && cachePort->cache->doMasterRequest()) + { + //Still more to issue, rerequest in 1 cycle + pkt = NULL; + this->schedule(curTick+1); + } + } else + { pkt = cachePort->cache->getCoherencePacket(); - bool success = cachePort->sendTiming(pkt); - cachePort->cache->sendResult(pkt, success); + cachePort->sendTiming(pkt); + } return; } //Know the packet to send, no need to mark in service (must succed) |