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Diffstat (limited to 'src/mem/cache/base_cache.cc')
-rw-r--r--src/mem/cache/base_cache.cc28
1 files changed, 24 insertions, 4 deletions
diff --git a/src/mem/cache/base_cache.cc b/src/mem/cache/base_cache.cc
index 599958222..c26d7782b 100644
--- a/src/mem/cache/base_cache.cc
+++ b/src/mem/cache/base_cache.cc
@@ -42,7 +42,7 @@ using namespace std;
BaseCache::CachePort::CachePort(const std::string &_name, BaseCache *_cache,
bool _isCpuSide)
- : Port(_name), cache(_cache), isCpuSide(_isCpuSide)
+ : Port(_name, _cache), cache(_cache), isCpuSide(_isCpuSide)
{
blocked = false;
waitingOnRetry = false;
@@ -140,6 +140,9 @@ BaseCache::CachePort::recvRetry()
}
waitingOnRetry = false;
}
+ // Check if we're done draining once this list is empty
+ if (drainList.empty())
+ cache->checkDrain();
}
else if (!isCpuSide)
{
@@ -338,6 +341,10 @@ BaseCache::CacheEvent::process()
cachePort->drainList.push_back(pkt);
cachePort->waitingOnRetry = true;
}
+
+ // Check if we're done draining once this list is empty
+ if (cachePort->drainList.empty())
+ cachePort->cache->checkDrain();
}
const char *
@@ -357,9 +364,7 @@ BaseCache::getPort(const std::string &if_name, int idx)
}
else if (if_name == "functional")
{
- if(cpuSidePort == NULL)
- cpuSidePort = new CachePort(name() + "-cpu_side_port", this, true);
- return cpuSidePort;
+ return new CachePort(name() + "-cpu_side_port", this, true);
}
else if (if_name == "cpu_side")
{
@@ -601,3 +606,18 @@ BaseCache::regStats()
;
}
+
+unsigned int
+BaseCache::drain(Event *de)
+{
+ // Set status
+ if (!canDrain()) {
+ drainEvent = de;
+
+ changeState(SimObject::Draining);
+ return 1;
+ }
+
+ changeState(SimObject::Drained);
+ return 0;
+}