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-rw-r--r--src/mem/cache/base_cache.hh12
1 files changed, 11 insertions, 1 deletions
diff --git a/src/mem/cache/base_cache.hh b/src/mem/cache/base_cache.hh
index e0f12940f..41c28f3a1 100644
--- a/src/mem/cache/base_cache.hh
+++ b/src/mem/cache/base_cache.hh
@@ -112,6 +112,8 @@ class BaseCache : public MemObject
bool isCpuSide;
+ bool waitingOnRetry;
+
std::list<Packet *> drainList;
Packet *cshrRetry;
@@ -465,7 +467,7 @@ class BaseCache : public MemObject
*/
void setMasterRequest(RequestCause cause, Tick time)
{
- if (!doMasterRequest())
+ if (!doMasterRequest() && memSidePort->drainList.empty())
{
BaseCache::CacheEvent * reqCpu = new BaseCache::CacheEvent(memSidePort);
reqCpu->schedule(time);
@@ -527,6 +529,10 @@ class BaseCache : public MemObject
CacheEvent *reqCpu = new CacheEvent(cpuSidePort, pkt);
reqCpu->schedule(time);
}
+ else {
+ if (pkt->cmd == Packet::Writeback) delete pkt->req;
+ delete pkt;
+ }
}
/**
@@ -543,6 +549,10 @@ class BaseCache : public MemObject
CacheEvent *reqCpu = new CacheEvent(cpuSidePort, pkt);
reqCpu->schedule(time);
}
+ else {
+ if (pkt->cmd == Packet::Writeback) delete pkt->req;
+ delete pkt;
+ }
}
/**