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Diffstat (limited to 'src/mem/cache/base_cache.hh')
-rw-r--r--src/mem/cache/base_cache.hh27
1 files changed, 16 insertions, 11 deletions
diff --git a/src/mem/cache/base_cache.hh b/src/mem/cache/base_cache.hh
index ee871c1c4..0f2baa306 100644
--- a/src/mem/cache/base_cache.hh
+++ b/src/mem/cache/base_cache.hh
@@ -117,13 +117,22 @@ class BaseCache : public MemObject
std::list<std::pair<Tick,PacketPtr> > transmitList;
};
- struct CacheEvent : public Event
+ struct RequestEvent : public Event
{
CachePort *cachePort;
PacketPtr pkt;
- bool newResponse;
- CacheEvent(CachePort *_cachePort, bool response);
+ RequestEvent(CachePort *_cachePort, Tick when);
+ void process();
+ const char *description();
+ };
+
+ struct ResponseEvent : public Event
+ {
+ CachePort *cachePort;
+ PacketPtr pkt;
+
+ ResponseEvent(CachePort *_cachePort);
void process();
const char *description();
};
@@ -132,8 +141,8 @@ class BaseCache : public MemObject
CachePort *cpuSidePort;
CachePort *memSidePort;
- CacheEvent *sendEvent;
- CacheEvent *memSendEvent;
+ ResponseEvent *sendEvent;
+ ResponseEvent *memSendEvent;
private:
void recvStatusChange(Port::Status status, bool isCpuSide)
@@ -432,9 +441,7 @@ class BaseCache : public MemObject
{
if (!doMasterRequest() && !memSidePort->waitingOnRetry)
{
- BaseCache::CacheEvent * reqCpu =
- new BaseCache::CacheEvent(memSidePort, false);
- reqCpu->schedule(time);
+ new RequestEvent(memSidePort, time);
}
uint8_t flag = 1<<cause;
masterRequests |= flag;
@@ -469,9 +476,7 @@ class BaseCache : public MemObject
{
if (!doSlaveRequest() && !cpuSidePort->waitingOnRetry)
{
- BaseCache::CacheEvent * reqCpu =
- new BaseCache::CacheEvent(cpuSidePort, false);
- reqCpu->schedule(time);
+ new RequestEvent(cpuSidePort, time);
}
uint8_t flag = 1<<cause;
slaveRequests |= flag;