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Diffstat (limited to 'src/mem/cache/base_cache.hh')
| -rw-r--r-- | src/mem/cache/base_cache.hh | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mem/cache/base_cache.hh b/src/mem/cache/base_cache.hh index fcc040bd9..46414974b 100644 --- a/src/mem/cache/base_cache.hh +++ b/src/mem/cache/base_cache.hh @@ -126,7 +126,7 @@ class BaseCache : public MemObject void requestBus(RequestCause cause, Tick time) { - DPRINTF(Cache, "Asserting bus request for cause %d\n", cause); + DPRINTF(CachePort, "Asserting bus request for cause %d\n", cause); if (!waitingOnRetry) { schedSendEvent(time); } |