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-rw-r--r--src/mem/cache/base_cache.hh14
1 files changed, 11 insertions, 3 deletions
diff --git a/src/mem/cache/base_cache.hh b/src/mem/cache/base_cache.hh
index 455e13d9c..7a9e57430 100644
--- a/src/mem/cache/base_cache.hh
+++ b/src/mem/cache/base_cache.hh
@@ -116,7 +116,6 @@ class BaseCache : public MemObject
std::list<Packet *> drainList;
- Packet *cshrRetry;
};
struct CacheEvent : public Event
@@ -188,6 +187,12 @@ class BaseCache : public MemObject
fatal("No implementation");
}
+ virtual void sendCoherenceResult(Packet* &pkt, MSHR* mshr, bool success)
+ {
+
+ fatal("No implementation");
+ }
+
/**
* Bit vector of the blocking reasons for the access path.
* @sa #BlockedCause
@@ -489,10 +494,13 @@ class BaseCache : public MemObject
*/
void setSlaveRequest(RequestCause cause, Tick time)
{
+ if (!doSlaveRequest() && !cpuSidePort->waitingOnRetry)
+ {
+ BaseCache::CacheEvent * reqCpu = new BaseCache::CacheEvent(cpuSidePort);
+ reqCpu->schedule(time);
+ }
uint8_t flag = 1<<cause;
slaveRequests |= flag;
- assert("Implement\n" && 0);
-// si->pktuest(time);
}
/**