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-rw-r--r--src/mem/cache/base_cache.hh6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/mem/cache/base_cache.hh b/src/mem/cache/base_cache.hh
index 0d1bfdfdb..7f0cb56f2 100644
--- a/src/mem/cache/base_cache.hh
+++ b/src/mem/cache/base_cache.hh
@@ -488,7 +488,7 @@ class BaseCache : public MemObject
/**
* Send a response to the slave interface.
- * @param req The request being responded to.
+ * @param pkt The request being responded to.
* @param time The time the response is ready.
*/
void respond(Packet *pkt, Tick time)
@@ -501,7 +501,7 @@ class BaseCache : public MemObject
/**
* Send a reponse to the slave interface and calculate miss latency.
- * @param req The request to respond to.
+ * @param pkt The request to respond to.
* @param time The time the response is ready.
*/
void respondToMiss(Packet *pkt, Tick time)
@@ -517,7 +517,7 @@ class BaseCache : public MemObject
/**
* Suppliess the data if cache to cache transfers are enabled.
- * @param req The bus transaction to fulfill.
+ * @param pkt The bus transaction to fulfill.
*/
void respondToSnoop(Packet *pkt)
{