diff options
Diffstat (limited to 'src/mem/cache/blk.hh')
| -rw-r--r-- | src/mem/cache/blk.hh | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/src/mem/cache/blk.hh b/src/mem/cache/blk.hh index c4ec12ff3..93189bd97 100644 --- a/src/mem/cache/blk.hh +++ b/src/mem/cache/blk.hh @@ -136,7 +136,7 @@ class CacheBlk : public ReplaceableEntry // check for matching execution context, and an address that // is within the lock - bool matches(const RequestPtr req) const + bool matches(const RequestPtr &req) const { Addr req_low = req->getPaddr(); Addr req_high = req_low + req->getSize() -1; @@ -145,7 +145,7 @@ class CacheBlk : public ReplaceableEntry } // check if a request is intersecting and thus invalidating the lock - bool intersects(const RequestPtr req) const + bool intersects(const RequestPtr &req) const { Addr req_low = req->getPaddr(); Addr req_high = req_low + req->getSize() - 1; @@ -153,7 +153,7 @@ class CacheBlk : public ReplaceableEntry return (req_low <= highAddr) && (req_high >= lowAddr); } - Lock(const RequestPtr req) + Lock(const RequestPtr &req) : contextId(req->contextId()), lowAddr(req->getPaddr()), highAddr(lowAddr + req->getSize() - 1) @@ -285,7 +285,7 @@ class CacheBlk : public ReplaceableEntry * Clear the any load lock that intersect the request, and is from * a different context. */ - void clearLoadLocks(RequestPtr req) + void clearLoadLocks(const RequestPtr &req) { auto l = lockList.begin(); while (l != lockList.end()) { @@ -357,7 +357,7 @@ class CacheBlk : public ReplaceableEntry if (!pkt->isLLSC() && lockList.empty()) return true; - RequestPtr req = pkt->req; + const RequestPtr &req = pkt->req; if (pkt->isLLSC()) { // it's a store conditional... have to check for matching |