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-rw-r--r--src/mem/cache/cache.cc10
1 files changed, 2 insertions, 8 deletions
diff --git a/src/mem/cache/cache.cc b/src/mem/cache/cache.cc
index 15c2b7a54..c3f289123 100644
--- a/src/mem/cache/cache.cc
+++ b/src/mem/cache/cache.cc
@@ -191,14 +191,8 @@ Cache::satisfyCpuSideRequest(PacketPtr pkt, CacheBlk *blk,
assert(pkt->hasRespData());
pkt->setDataFromBlock(blk->data, blkSize);
- // determine if this read is from a (coherent) cache, or not
- // by looking at the command type; we could potentially add a
- // packet attribute such as 'FromCache' to make this check a
- // bit cleaner
- if (pkt->cmd == MemCmd::ReadExReq ||
- pkt->cmd == MemCmd::ReadSharedReq ||
- pkt->cmd == MemCmd::ReadCleanReq ||
- pkt->cmd == MemCmd::SCUpgradeFailReq) {
+ // determine if this read is from a (coherent) cache or not
+ if (pkt->fromCache()) {
assert(pkt->getSize() == blkSize);
// special handling for coherent block requests from
// upper-level caches