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-rw-r--r--src/mem/cache/cache.hh17
1 files changed, 14 insertions, 3 deletions
diff --git a/src/mem/cache/cache.hh b/src/mem/cache/cache.hh
index 1ed138bb5..8d30ed443 100644
--- a/src/mem/cache/cache.hh
+++ b/src/mem/cache/cache.hh
@@ -1,4 +1,16 @@
/*
+ * Copyright (c) 2012 ARM Limited
+ * All rights reserved.
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright (c) 2002-2005 The Regents of The University of Michigan
* All rights reserved.
*
@@ -225,10 +237,9 @@ class Cache : public BaseCache
/**
* Performs the access specified by the request.
* @param pkt The request to perform.
- * @return The result of the access.
+ * @param fromCpuSide from the CPU side port or the memory side port
*/
- void functionalAccess(PacketPtr pkt, CachePort *incomingPort,
- CachePort *otherSidePort);
+ void functionalAccess(PacketPtr pkt, bool fromCpuSide);
/**
* Handles a response (cache line fill/write ack) from the bus.