summaryrefslogtreecommitdiff
path: root/src/mem/cache/cache.hh
diff options
context:
space:
mode:
Diffstat (limited to 'src/mem/cache/cache.hh')
-rw-r--r--src/mem/cache/cache.hh12
1 files changed, 12 insertions, 0 deletions
diff --git a/src/mem/cache/cache.hh b/src/mem/cache/cache.hh
index 5df725683..6b062ef40 100644
--- a/src/mem/cache/cache.hh
+++ b/src/mem/cache/cache.hh
@@ -278,6 +278,18 @@ class Cache : public BaseCache
*/
bool invalidateVisitor(BlkType &blk);
+ /**
+ * Flush a cache line due to an uncacheable memory access to the
+ * line.
+ *
+ * @note This shouldn't normally happen, but we need to handle it
+ * since some architecture models don't implement cache
+ * maintenance operations. We won't even try to get a decent
+ * timing here since the line should have been flushed earlier by
+ * a cache maintenance operation.
+ */
+ void uncacheableFlush(PacketPtr pkt);
+
public:
/** Instantiates a basic cache object. */
Cache(const Params *p, TagStore *tags);