1 files changed, 22 insertions, 0 deletions
diff --git a/src/mem/cache/cache.hh b/src/mem/cache/cache.hh
index be81736aa..5df725683 100644
--- a/src/mem/cache/cache.hh
+++ b/src/mem/cache/cache.hh
@@ -76,6 +76,7 @@ class Cache : public BaseCache
     typedef typename TagStore::BlkList BlkList;
 
   protected:
+    typedef CacheBlkVisitorWrapper<Cache<TagStore>, BlkType> WrappedBlkVisitor;
 
     /**
      * The CPU-side port extends the base cache slave port with access
@@ -256,6 +257,27 @@ class Cache : public BaseCache
      */
     PacketPtr writebackBlk(BlkType *blk);
 
+
+    void memWriteback();
+    void memInvalidate();
+    bool isDirty() const;
+
+    /**
+     * Cache block visitor that writes back dirty cache blocks using
+     * functional writes.
+     *
+     * \return Always returns true.
+     */
+    bool writebackVisitor(BlkType &blk);
+    /**
+     * Cache block visitor that invalidates all blocks in the cache.
+     *
+     * @warn Dirty cache lines will not be written back to memory.
+     *
+     * \return Always returns true.
+     */
+    bool invalidateVisitor(BlkType &blk);
+
   public:
     /** Instantiates a basic cache object. */
     Cache(const Params *p, TagStore *tags);