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-rw-r--r--src/mem/cache/cache.hh5
1 files changed, 5 insertions, 0 deletions
diff --git a/src/mem/cache/cache.hh b/src/mem/cache/cache.hh
index 0ee1e353a..12fb3b0f0 100644
--- a/src/mem/cache/cache.hh
+++ b/src/mem/cache/cache.hh
@@ -181,6 +181,11 @@ class Cache : public BaseCache
const bool doFastWrites;
/**
+ * Turn line-sized writes into WriteInvalidate transactions.
+ */
+ void promoteWholeLineWrites(PacketPtr pkt);
+
+ /**
* Notify the prefetcher on every access, not just misses.
*/
const bool prefetchOnAccess;