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-rw-r--r--src/mem/cache/cache_impl.hh3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index e4a6f3c24..5cfe7c0cf 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -917,6 +917,9 @@ Cache<TagStore>::recvAtomic(PacketPtr pkt)
if (pkt->cmd == MemCmd::WriteInvalidateReq) {
memSidePort->sendAtomic(pkt); // complete writeback
if (isTopLevel) {
+ // @todo Static analysis suggests this can actually happen
+ assert(blk);
+
// top level caches allocate and write the data
assert(blk->isDirty());
assert(!blk->isWritable());