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-rw-r--r--src/mem/cache/cache_impl.hh10
1 files changed, 10 insertions, 0 deletions
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index c4acc03e7..d8afcb009 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -593,6 +593,8 @@ Cache<TagStore,Buffering,Coherence>::probe(Packet * &pkt, bool update,
if (pkt->isWrite()) {
memcpy(pkt_data, write_data, data_size);
} else {
+ pkt->flags |= SATISFIED;
+ pkt->result = Packet::Success;
memcpy(write_data, pkt_data, data_size);
}
}
@@ -626,11 +628,19 @@ Cache<TagStore,Buffering,Coherence>::probe(Packet * &pkt, bool update,
if (pkt->isWrite()) {
memcpy(pkt_data, write_data, data_size);
} else {
+ pkt->flags |= SATISFIED;
+ pkt->result = Packet::Success;
memcpy(write_data, pkt_data, data_size);
}
}
}
+ if (pkt->isRead()
+ && pkt->result != Packet::Success
+ && otherSidePort == memSidePort) {
+ otherSidePort->sendFunctional(pkt);
+ assert(pkt->result == Packet::Success);
+ }
return 0;
} else if (!blk) {
// update the cache state and statistics