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-rw-r--r--src/mem/cache/cache_impl.hh4
1 files changed, 1 insertions, 3 deletions
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index a447ae3d5..56e7a4d58 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -53,8 +53,6 @@
#include "sim/sim_events.hh" // for SimExitEvent
-using namespace std;
-
template<class TagStore, class Buffering, class Coherence>
bool
Cache<TagStore,Buffering,Coherence>::
@@ -501,7 +499,7 @@ Cache<TagStore,Buffering,Coherence>::probe(Packet * &pkt, bool update)
MSHR* mshr = missQueue->findMSHR(blk_addr, pkt->req->getAsid());
// There can be many matching outstanding writes.
- vector<MSHR*> writes;
+ std::vector<MSHR*> writes;
missQueue->findWrites(blk_addr, pkt->req->getAsid(), writes);
if (!update) {