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-rw-r--r--src/mem/cache/cache_impl.hh4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index ff35a0749..dac2b93a4 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -206,7 +206,7 @@ Cache<TagStore,Coherence>::handleAccess(PacketPtr &pkt, int & lat,
// complete miss (no matching block)
if (pkt->req->isLocked() && pkt->isWrite()) {
// miss on store conditional... just give up now
- pkt->req->setScResult(0);
+ pkt->req->setExtraData(0);
pkt->flags |= SATISFIED;
}
}
@@ -1147,7 +1147,7 @@ Cache<TagStore,Coherence>::CpuSidePort::recvTiming(PacketPtr pkt)
}
if (pkt->isWrite() && (pkt->req->isLocked())) {
- pkt->req->setScResult(1);
+ pkt->req->setExtraData(1);
}
myCache()->access(pkt);
return true;