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-rw-r--r--src/mem/cache/cache_impl.hh11
1 files changed, 10 insertions, 1 deletions
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index dac2b93a4..056f6033f 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -1100,7 +1100,7 @@ Cache<TagStore,Coherence>::getPort(const std::string &if_name, int idx)
}
else if (if_name == "functional")
{
- return new CpuSidePort(name() + "-cpu_side_port", this);
+ return new CpuSidePort(name() + "-cpu_side_funcport", this);
}
else if (if_name == "cpu_side")
{
@@ -1121,6 +1121,15 @@ Cache<TagStore,Coherence>::getPort(const std::string &if_name, int idx)
else panic("Port name %s unrecognized\n", if_name);
}
+template<class TagStore, class Coherence>
+void
+Cache<TagStore,Coherence>::deletePortRefs(Port *p)
+{
+ if (cpuSidePort == p || memSidePort == p)
+ panic("Can only delete functional ports\n");
+ // nothing else to do
+}
+
template<class TagStore, class Coherence>
bool