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-rw-r--r--src/mem/cache/cache_impl.hh4
1 files changed, 4 insertions, 0 deletions
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index e1aed8b0c..e9a40a741 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -1443,6 +1443,10 @@ Cache<TagStore>::getNextMSHR()
mshr_misses[pkt->cmdToIndex()][0/*pkt->req->threadId()*/]++;
// Don't request bus, since we already have it
return allocateMissBuffer(pkt, curTick(), false);
+ } else {
+ // free the request and packet
+ delete pkt->req;
+ delete pkt;
}
}
}