diff options
Diffstat (limited to 'src/mem/cache/cache_impl.hh')
| -rw-r--r-- | src/mem/cache/cache_impl.hh | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh index 56352c110..a7f96603e 100644 --- a/src/mem/cache/cache_impl.hh +++ b/src/mem/cache/cache_impl.hh @@ -1140,6 +1140,18 @@ Cache<TagStore,Coherence>::deletePortRefs(Port *p) template<class TagStore, class Coherence> +void +Cache<TagStore,Coherence>::CpuSidePort:: +getDeviceAddressRanges(AddrRangeList &resp, bool &snoop) +{ + // CPU side port doesn't snoop; it's a target only. + bool dummy; + otherPort->getPeerAddressRanges(resp, dummy); + snoop = false; +} + + +template<class TagStore, class Coherence> bool Cache<TagStore,Coherence>::CpuSidePort::recvTiming(PacketPtr pkt) { @@ -1261,6 +1273,18 @@ Cache<TagStore,Coherence>::CpuSidePort::recvFunctional(PacketPtr pkt) template<class TagStore, class Coherence> +void +Cache<TagStore,Coherence>::MemSidePort:: +getDeviceAddressRanges(AddrRangeList &resp, bool &snoop) +{ + // Memory-side port always snoops. + bool dummy; + otherPort->getPeerAddressRanges(resp, dummy); + snoop = true; +} + + +template<class TagStore, class Coherence> bool Cache<TagStore,Coherence>::MemSidePort::recvTiming(PacketPtr pkt) { |