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Diffstat (limited to 'src/mem/cache/coherence/simple_coherence.hh')
-rw-r--r--src/mem/cache/coherence/simple_coherence.hh7
1 files changed, 4 insertions, 3 deletions
diff --git a/src/mem/cache/coherence/simple_coherence.hh b/src/mem/cache/coherence/simple_coherence.hh
index a1fd33080..1c89c703a 100644
--- a/src/mem/cache/coherence/simple_coherence.hh
+++ b/src/mem/cache/coherence/simple_coherence.hh
@@ -131,7 +131,7 @@ class SimpleCoherence
//Got rid of, there could be an MSHR, but it can't be in service
if (blk != NULL)
{
- if (pkt->cmd != Packet::Writeback) {
+ if (pkt->cmd != MemCmd::Writeback) {
return protocol->handleBusRequest(cache, pkt, blk, mshr,
new_state);
}
@@ -148,9 +148,10 @@ class SimpleCoherence
* @param state The current state of the cache block.
* @return The proper bus command, as determined by the protocol.
*/
- Packet::Command getBusCmd(Packet::Command &cmd, CacheBlk::State state)
+ MemCmd getBusCmd(MemCmd cmd,
+ CacheBlk::State state)
{
- if (cmd == Packet::Writeback) return Packet::Writeback;
+ if (cmd == MemCmd::Writeback) return MemCmd::Writeback;
return protocol->getBusCmd(cmd, state);
}