diff options
Diffstat (limited to 'src/mem/cache/coherence')
| -rw-r--r-- | src/mem/cache/coherence/coherence_protocol.hh | 4 | ||||
| -rw-r--r-- | src/mem/cache/coherence/simple_coherence.hh | 6 | ||||
| -rw-r--r-- | src/mem/cache/coherence/uni_coherence.hh | 11 |
3 files changed, 10 insertions, 11 deletions
diff --git a/src/mem/cache/coherence/coherence_protocol.hh b/src/mem/cache/coherence/coherence_protocol.hh index 4f6520552..21351ace4 100644 --- a/src/mem/cache/coherence/coherence_protocol.hh +++ b/src/mem/cache/coherence/coherence_protocol.hh @@ -26,6 +26,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * Authors: Erik Hallnor + * Ron Dreslinski * Steve Reinhardt */ @@ -40,7 +41,6 @@ #include "sim/sim_object.hh" #include "mem/packet.hh" -#include "mem/mem_cmd.hh" #include "mem/cache/cache_blk.hh" #include "base/statistics.hh" @@ -89,7 +89,7 @@ class CoherenceProtocol : public SimObject * @param oldState The current block state. * @return The new state. */ - CacheBlk::State getNewState(const Packet * &pkt, + CacheBlk::State getNewState(Packet * &pkt, CacheBlk::State oldState); /** diff --git a/src/mem/cache/coherence/simple_coherence.hh b/src/mem/cache/coherence/simple_coherence.hh index 195674590..ca9d18beb 100644 --- a/src/mem/cache/coherence/simple_coherence.hh +++ b/src/mem/cache/coherence/simple_coherence.hh @@ -26,6 +26,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * Authors: Erik Hallnor + * Ron Dreslinski */ /** @@ -39,7 +40,6 @@ #include <string> #include "mem/packet.hh" -#include "mem/mem_cmd.hh" #include "mem/cache/cache_blk.hh" #include "mem/cache/miss/mshr_queue.hh" #include "mem/cache/coherence/coherence_protocol.hh" @@ -119,7 +119,7 @@ class SimpleCoherence //Got rid of, there could be an MSHR, but it can't be in service if (blk != NULL) { - if (pkt->cmd != Writeback) { + if (pkt->cmd != Packet::Writeback) { return protocol->handleBusRequest(cache, pkt, blk, mshr, new_state); } @@ -138,7 +138,7 @@ class SimpleCoherence */ Packet::Command getBusCmd(Packet::Command &cmd, CacheBlk::State state) { - if (cmd == Writeback) return Writeback; + if (cmd == Packet::Writeback) return Packet::Writeback; return protocol->getBusCmd(cmd, state); } diff --git a/src/mem/cache/coherence/uni_coherence.hh b/src/mem/cache/coherence/uni_coherence.hh index b64f6c931..4e895997f 100644 --- a/src/mem/cache/coherence/uni_coherence.hh +++ b/src/mem/cache/coherence/uni_coherence.hh @@ -34,7 +34,6 @@ #include "base/trace.hh" #include "mem/cache/cache_blk.hh" #include "mem/cache/miss/mshr_queue.hh" -#include "mem/mem_cmd.hh" #include "mem/packet.hh" class BaseCache; @@ -79,11 +78,11 @@ class UniCoherence */ Packet::Command getBusCmd(Packet::Command &cmd, CacheBlk::State state) { - if (cmd == Hard_Prefetch && state) + if (cmd == Packet::HardPFReq && state) warn("Trying to issue a prefetch to a block we already have\n"); - if (cmd == Writeback) - return Writeback; - return Read; + if (cmd == Packet::Writeback) + return Packet::Writeback; + return Packet::ReadReq; } /** @@ -96,7 +95,7 @@ class UniCoherence { if (pkt->senderState) //Blocking Buffers don't get mshrs { - if (pkt->senderState->originalCmd == Hard_Prefetch) { + if (((MSHR *)(pkt->senderState))->originalCmd == Packet::HardPFReq) { DPRINTF(HWPrefetch, "Marking a hardware prefetch as such in the state\n"); return BlkHWPrefetched | BlkValid | BlkWritable; } |