diff options
Diffstat (limited to 'src/mem/cache/miss/mshr.hh')
-rw-r--r-- | src/mem/cache/miss/mshr.hh | 77 |
1 files changed, 56 insertions, 21 deletions
diff --git a/src/mem/cache/miss/mshr.hh b/src/mem/cache/miss/mshr.hh index d0410acda..b38b69c52 100644 --- a/src/mem/cache/miss/mshr.hh +++ b/src/mem/cache/miss/mshr.hh @@ -36,22 +36,39 @@ #ifndef __MSHR_HH__ #define __MSHR_HH__ -#include "mem/packet.hh" #include <list> -#include <deque> -class MSHR; +#include "mem/packet.hh" + +class CacheBlk; +class MSHRQueue; /** * Miss Status and handling Register. This class keeps all the information * needed to handle a cache miss including a list of target requests. */ -class MSHR { +class MSHR : public Packet::SenderState +{ + public: + + class Target { + public: + Tick time; //!< Time when request was received (for stats) + PacketPtr pkt; //!< Pending request packet. + bool cpuSide; //!< Did request come from cpu side or mem side? + + bool isCpuSide() { return cpuSide; } + + Target(PacketPtr _pkt, bool _cpuSide, Tick _time = curTick) + : time(_time), pkt(_pkt), cpuSide(_cpuSide) + {} + }; + /** Defines the Data structure of the MSHR targetlist. */ - typedef std::list<PacketPtr> TargetList; + typedef std::list<Target> TargetList; /** Target list iterator. */ - typedef std::list<PacketPtr>::iterator TargetListIterator; + typedef std::list<Target>::iterator TargetListIterator; /** A list of MSHRs. */ typedef std::list<MSHR *> List; /** MSHR list iterator. */ @@ -59,20 +76,35 @@ class MSHR { /** MSHR list const_iterator. */ typedef List::const_iterator ConstIterator; - /** Address of the miss. */ + /** Pointer to queue containing this MSHR. */ + MSHRQueue *queue; + + /** Address of the request. */ Addr addr; - /** Adress space id of the miss. */ - short asid; + + /** Size of the request. */ + int size; + + /** Data associated with the request (if a write). */ + uint8_t *writeData; + /** True if the request has been sent to the bus. */ bool inService; + + /** True if we will be putting the returned block in the cache */ + bool isCacheFill; + /** True if we need to get an exclusive copy of the block. */ + bool needsExclusive; + /** True if the request is uncacheable */ + bool _isUncacheable; + + /** True if the request that has been sent to the bus is for en + * exclusive copy. */ + bool inServiceForExclusive; /** Thread number of the miss. */ - int threadNum; - /** The request that is forwarded to the next level of the hierarchy. */ - PacketPtr pkt; + short threadNum; /** The number of currently allocated targets. */ short ntargets; - /** The original requesting command. */ - MemCmd originalCmd; /** Order number of assigned by the miss queue. */ uint64_t order; @@ -81,6 +113,7 @@ class MSHR { * @sa MissQueue, MSHRQueue::readyList */ Iterator readyIter; + /** * Pointer to this MSHR on the allocated list. * @sa MissQueue, MSHRQueue::allocatedList @@ -92,6 +125,9 @@ private: TargetList targets; public: + + bool isUncacheable() { return _isUncacheable; } + /** * Allocate a miss to this MSHR. * @param cmd The requesting command. @@ -100,14 +136,13 @@ public: * @param size The number of bytes to request. * @param pkt The original miss. */ - void allocate(MemCmd cmd, Addr addr, int size, - PacketPtr &pkt); + void allocate(Addr addr, int size, PacketPtr pkt, bool isFill); /** * Allocate this MSHR as a buffer for the given request. * @param target The memory request to buffer. */ - void allocateAsBuffer(PacketPtr &target); + void allocateAsBuffer(PacketPtr target); /** * Mark this MSHR as free. @@ -118,7 +153,7 @@ public: * Add a request to the list of targets. * @param target The target. */ - void allocateTarget(PacketPtr &target); + void allocateTarget(PacketPtr target, bool cpuSide); /** A simple constructor. */ MSHR(); @@ -131,7 +166,7 @@ public: */ int getNumTargets() { - return(ntargets); + return ntargets; } /** @@ -147,9 +182,9 @@ public: * Returns a reference to the first target. * @return A pointer to the first target. */ - PacketPtr getTarget() + Target *getTarget() { - return targets.front(); + return &targets.front(); } /** |