diff options
Diffstat (limited to 'src/mem/cache/noncoherent_cache.cc')
| -rw-r--r-- | src/mem/cache/noncoherent_cache.cc | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/src/mem/cache/noncoherent_cache.cc b/src/mem/cache/noncoherent_cache.cc index b4ffed786..726c32f1c 100644 --- a/src/mem/cache/noncoherent_cache.cc +++ b/src/mem/cache/noncoherent_cache.cc @@ -148,7 +148,8 @@ NoncoherentCache::recvTimingReq(PacketPtr pkt) PacketPtr NoncoherentCache::createMissPacket(PacketPtr cpu_pkt, CacheBlk *blk, - bool needs_writable) const + bool needs_writable, + bool is_whole_line_write) const { // We also fill for writebacks from the coherent caches above us, // and they do not need responses @@ -173,7 +174,8 @@ Cycles NoncoherentCache::handleAtomicReqMiss(PacketPtr pkt, CacheBlk *&blk, PacketList &writebacks) { - PacketPtr bus_pkt = createMissPacket(pkt, blk, true); + PacketPtr bus_pkt = createMissPacket(pkt, blk, true, + pkt->isWholeLineWrite(blkSize)); DPRINTF(Cache, "Sending an atomic %s\n", bus_pkt->print()); Cycles latency = ticksToCycles(memSidePort.sendAtomic(bus_pkt)); |