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path: root/src/mem/cache/prefetch/Prefetcher.py
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Diffstat (limited to 'src/mem/cache/prefetch/Prefetcher.py')
-rw-r--r--src/mem/cache/prefetch/Prefetcher.py4
1 files changed, 4 insertions, 0 deletions
diff --git a/src/mem/cache/prefetch/Prefetcher.py b/src/mem/cache/prefetch/Prefetcher.py
index e590410ae..af67f40b6 100644
--- a/src/mem/cache/prefetch/Prefetcher.py
+++ b/src/mem/cache/prefetch/Prefetcher.py
@@ -45,6 +45,7 @@ from m5.proxy import *
class BasePrefetcher(ClockedObject):
type = 'BasePrefetcher'
abstract = True
+ cxx_header = "mem/cache/prefetch/base.hh"
size = Param.Int(100,
"Number of entries in the hardware prefetch queue")
cross_pages = Param.Bool(False,
@@ -63,14 +64,17 @@ class BasePrefetcher(ClockedObject):
class GHBPrefetcher(BasePrefetcher):
type = 'GHBPrefetcher'
cxx_class = 'GHBPrefetcher'
+ cxx_header = "mem/cache/prefetch/ghb.hh"
class StridePrefetcher(BasePrefetcher):
type = 'StridePrefetcher'
cxx_class = 'StridePrefetcher'
+ cxx_header = "mem/cache/prefetch/stride.hh"
class TaggedPrefetcher(BasePrefetcher):
type = 'TaggedPrefetcher'
cxx_class = 'TaggedPrefetcher'
+ cxx_header = "mem/cache/prefetch/tagged.hh"