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Diffstat (limited to 'src/mem/cache/prefetch/Prefetcher.py')
| -rw-r--r-- | src/mem/cache/prefetch/Prefetcher.py | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mem/cache/prefetch/Prefetcher.py b/src/mem/cache/prefetch/Prefetcher.py index bae235d84..df547ed42 100644 --- a/src/mem/cache/prefetch/Prefetcher.py +++ b/src/mem/cache/prefetch/Prefetcher.py @@ -76,6 +76,8 @@ class BasePrefetcher(ClockedObject): on_inst = Param.Bool(True, "Notify prefetcher on instruction accesses") prefetch_on_access = Param.Bool(Parent.prefetch_on_access, "Notify the hardware prefetcher on every access (not just misses)") + use_virtual_addresses = Param.Bool(False, + "Use virtual addresses for prefetching") _events = [] def addEvent(self, newObject): |