summaryrefslogtreecommitdiff
path: root/src/mem/cache/prefetch/base.hh
diff options
context:
space:
mode:
Diffstat (limited to 'src/mem/cache/prefetch/base.hh')
-rw-r--r--src/mem/cache/prefetch/base.hh20
1 files changed, 15 insertions, 5 deletions
diff --git a/src/mem/cache/prefetch/base.hh b/src/mem/cache/prefetch/base.hh
index 953852c38..fc0dd0b36 100644
--- a/src/mem/cache/prefetch/base.hh
+++ b/src/mem/cache/prefetch/base.hh
@@ -89,18 +89,28 @@ class BasePrefetcher : public ClockedObject
const Cycles latency;
/** The number of prefetches to issue */
- unsigned degree;
+ const unsigned degree;
/** If patterns should be found per context id */
- bool useMasterId;
+ const bool useMasterId;
/** Do we prefetch across page boundaries. */
- bool pageStop;
+ const bool pageStop;
/** Do we remove prefetches with later times than a new miss.*/
- bool serialSquash;
+ const bool serialSquash;
/** Do we prefetch on only data reads, or on inst reads as well. */
- bool onlyData;
+ const bool onlyData;
+
+ /** Do we trigger/train prefetch on cache misses only, or all accesses. */
+ const bool onMissOnly;
+
+ /** Do we trigger/train prefetch on reads only, or all accesses. */
+ const bool onReadOnly;
+
+ /** Do we tag prefetch's with PC addresses, allowing lower pc-based
+ prefetchers to prefetch on prefetch requests */
+ const bool onPrefetch;
/** System we belong to */
System* system;