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Diffstat (limited to 'src/mem/cache/prefetch/base.hh')
-rw-r--r--src/mem/cache/prefetch/base.hh23
1 files changed, 11 insertions, 12 deletions
diff --git a/src/mem/cache/prefetch/base.hh b/src/mem/cache/prefetch/base.hh
index 394c85c94..813d1b9a4 100644
--- a/src/mem/cache/prefetch/base.hh
+++ b/src/mem/cache/prefetch/base.hh
@@ -60,7 +60,6 @@
class BaseCache;
struct BasePrefetcherParams;
-class System;
class BasePrefetcher : public ClockedObject
{
@@ -90,26 +89,23 @@ class BasePrefetcher : public ClockedObject
/** log_2(block size of the parent cache). */
unsigned lBlkSize;
- /** System we belong to */
- System* system;
-
/** Only consult prefetcher on cache misses? */
- bool onMiss;
+ const bool onMiss;
/** Consult prefetcher on reads? */
- bool onRead;
+ const bool onRead;
/** Consult prefetcher on reads? */
- bool onWrite;
+ const bool onWrite;
/** Consult prefetcher on data accesses? */
- bool onData;
+ const bool onData;
/** Consult prefetcher on instruction accesses? */
- bool onInst;
+ const bool onInst;
/** Request id for prefetches */
- MasterID masterId;
+ const MasterID masterId;
const Addr pageBytes;
@@ -147,7 +143,7 @@ class BasePrefetcher : public ClockedObject
virtual ~BasePrefetcher() {}
- virtual void setCache(BaseCache *_cache);
+ void setCache(BaseCache *_cache);
/**
* Notify prefetcher of cache access (may be any access or just
@@ -159,7 +155,10 @@ class BasePrefetcher : public ClockedObject
virtual Tick nextPrefetchReadyTime() const = 0;
- virtual void regStats();
+ /**
+ * Register local statistics.
+ */
+ void regStats() override;
/**
* Register probe points for this object.