1 files changed, 7 insertions, 52 deletions

diff --git a/src/mem/cache/prefetch/ghb_prefetcher.hh b/src/mem/cache/prefetch/ghb_prefetcher.hh
index c558a3e64..f31b56dcf 100644
--- a/src/mem/cache/prefetch/ghb_prefetcher.hh
+++ b/src/mem/cache/prefetch/ghb_prefetcher.hh
@@ -30,31 +30,18 @@
 
 /**
  * @file
- * Describes a ghb prefetcher based on template policies.
+ * Describes a ghb prefetcher.
  */
 
 #ifndef __MEM_CACHE_PREFETCH_GHB_PREFETCHER_HH__
 #define __MEM_CACHE_PREFETCH_GHB_PREFETCHER_HH__
 
-#include "base/misc.hh" // fatal, panic, and warn
+#include "mem/cache/prefetch/base_prefetcher.hh"
 
-#include "mem/cache/prefetch/prefetcher.hh"
-
-/**
- * A template-policy based cache. The behavior of the cache can be altered by
- * supplying different template policies. TagStore handles all tag and data
- * storage @sa TagStore. MissBuffer handles all misses and writes/writebacks
- * @sa MissQueue. Coherence handles all coherence policy details @sa
- * UniCoherence, SimpleMultiCoherence.
- */
-template <class TagStore>
-class GHBPrefetcher : public Prefetcher<TagStore>
+class GHBPrefetcher : public BasePrefetcher
 {
   protected:
 
-    MissBuffer* mq;
-    TagStore* tags;
-
     Addr second_last_miss_addr[64/*MAX_CPUS*/];
     Addr last_miss_addr[64/*MAX_CPUS*/];
 
@@ -67,48 +54,16 @@ class GHBPrefetcher : public Prefetcher<TagStore>
     GHBPrefetcher(int size, bool pageStop, bool serialSquash,
                   bool cacheCheckPush, bool onlyData,
                   Tick latency, int degree, bool useCPUId)
-        :Prefetcher<TagStore>(size, pageStop, serialSquash,
-                                         cacheCheckPush, onlyData),
-         latency(latency), degree(degree), useCPUId(useCPUId)
+        : BasePrefetcher(size, pageStop, serialSquash,
+                         cacheCheckPush, onlyData),
+          latency(latency), degree(degree), useCPUId(useCPUId)
     {
     }
 
     ~GHBPrefetcher() {}
 
     void calculatePrefetch(PacketPtr &pkt, std::list<Addr> &addresses,
-                           std::list<Tick> &delays)
-    {
-        Addr blkAddr = pkt->getAddr() & ~(Addr)(this->blkSize-1);
-        int cpuID = pkt->req->getCpuNum();
-        if (!useCPUId) cpuID = 0;
-
-
-        int new_stride = blkAddr - last_miss_addr[cpuID];
-        int old_stride = last_miss_addr[cpuID] -
-                         second_last_miss_addr[cpuID];
-
-        second_last_miss_addr[cpuID] = last_miss_addr[cpuID];
-        last_miss_addr[cpuID] = blkAddr;
-
-        if (new_stride == old_stride) {
-            for (int d=1; d <= degree; d++) {
-                Addr newAddr = blkAddr + d * new_stride;
-                if (this->pageStop &&
-                    (blkAddr & ~(TheISA::VMPageSize - 1)) !=
-                    (newAddr & ~(TheISA::VMPageSize - 1)))
-                {
-                    //Spanned the page, so now stop
-                    this->pfSpanPage += degree - d + 1;
-                    return;
-                }
-                else
-                {
-                    addresses.push_back(newAddr);
-                    delays.push_back(latency);
-                }
-            }
-        }
-    }
+                           std::list<Tick> &delays);
 };
 
 #endif // __MEM_CACHE_PREFETCH_GHB_PREFETCHER_HH__