1 files changed, 51 insertions, 7 deletions
diff --git a/src/mem/cache/prefetch/stride_prefetcher.cc b/src/mem/cache/prefetch/stride_prefetcher.cc
index 2204871cc..8d957182a 100644
--- a/src/mem/cache/prefetch/stride_prefetcher.cc
+++ b/src/mem/cache/prefetch/stride_prefetcher.cc
@@ -34,15 +34,59 @@
  * Stride Prefetcher template instantiations.
  */
 
-#include "mem/cache/tags/cache_tags.hh"
+#include "mem/cache/prefetch/stride_prefetcher.hh"
 
-#include "mem/cache/tags/lru.hh"
+void
+StridePrefetcher::calculatePrefetch(PacketPtr &pkt, std::list<Addr> &addresses,
+                                    std::list<Tick> &delays)
+{
+//	Addr blkAddr = pkt->paddr & ~(Addr)(this->blkSize-1);
+    int cpuID = pkt->req->getCpuNum();
+    if (!useCPUId) cpuID = 0;
 
-#include "mem/cache/prefetch/stride_prefetcher.hh"
+    /* Scan Table for IAddr Match */
+/*	std::list<strideEntry*>::iterator iter;
+  for (iter=table[cpuID].begin();
+  iter !=table[cpuID].end();
+  iter++) {
+  if ((*iter)->IAddr == pkt->pc) break;
+  }
+
+  if (iter != table[cpuID].end()) {
+  //Hit in table
+
+  int newStride = blkAddr - (*iter)->MAddr;
+  if (newStride == (*iter)->stride) {
+  (*iter)->confidence++;
+  }
+  else {
+  (*iter)->stride = newStride;
+  (*iter)->confidence--;
+  }
 
-// Template Instantiations
-#ifndef DOXYGEN_SHOULD_SKIP_THIS
+  (*iter)->MAddr = blkAddr;
 
-template class StridePrefetcher<CacheTags<LRU> >;
+  for (int d=1; d <= degree; d++) {
+  Addr newAddr = blkAddr + d * newStride;
+  if (this->pageStop &&
+  (blkAddr & ~(TheISA::VMPageSize - 1)) !=
+  (newAddr & ~(TheISA::VMPageSize - 1)))
+  {
+  //Spanned the page, so now stop
+  this->pfSpanPage += degree - d + 1;
+  return;
+  }
+  else
+  {
+  addresses.push_back(newAddr);
+  delays.push_back(latency);
+  }
+  }
+  }
+  else {
+  //Miss in table
+  //Find lowest confidence and replace
 
-#endif //DOXYGEN_SHOULD_SKIP_THIS
+  }
+*/
+}