4 files changed, 17 insertions, 17 deletions

diff --git a/src/mem/cache/prefetch/base_prefetcher.cc b/src/mem/cache/prefetch/base_prefetcher.cc
index 7b2d57cd5..29da53746 100644
--- a/src/mem/cache/prefetch/base_prefetcher.cc
+++ b/src/mem/cache/prefetch/base_prefetcher.cc
@@ -36,6 +36,7 @@
 #include "base/trace.hh"
 #include "mem/cache/base_cache.hh"
 #include "mem/cache/prefetch/base_prefetcher.hh"
+#include "mem/request.hh"
 #include <list>
 
 BasePrefetcher::BasePrefetcher(int size, bool pageStop, bool serialSquash,
@@ -132,10 +133,10 @@ BasePrefetcher::getPacket()
 void
 BasePrefetcher::handleMiss(Packet * &pkt, Tick time)
 {
-    if (!pkt->req->isUncacheable() && !(pkt->isInstRead() && only_data))
+    if (!pkt->req->isUncacheable() && !(pkt->req->isInstRead() && only_data))
     {
         //Calculate the blk address
-        Addr blkAddr = pkt->paddr & ~(Addr)(blkSize-1);
+        Addr blkAddr = pkt->getAddr() & ~(Addr)(blkSize-1);
 
         //Check if miss is in pfq, if so remove it
         std::list<Packet *>::iterator iter = inPrefetch(blkAddr);
@@ -177,15 +178,14 @@ BasePrefetcher::handleMiss(Packet * &pkt, Tick time)
             //temp calc this here...
             pfIdentified++;
             //create a prefetch memreq
+            Request * prefetchReq = new Request(*addr, blkSize, 0);
             Packet * prefetch;
-            prefetch = new Packet();
-            prefetch->paddr = (*addr);
-            prefetch->size = blkSize;
-            prefetch->cmd = Hard_Prefetch;
-            prefetch->xc = pkt->xc;
-            prefetch->data = new uint8_t[blkSize];
-            prefetch->req->asid = pkt->req->asid;
-            prefetch->req->setThreadNum() = pkt->req->getThreadNum();
+            prefetch = new Packet(prefetchReq, Packet::HardPFReq, -1);
+            uint8_t *new_data = new uint8_t[blkSize];
+            prefetch->dataDynamicArray<uint8_t>(new_data);
+            prefetch->req->setThreadContext(pkt->req->getCpuNum(),
+                                            pkt->req->getThreadNum());
+
             prefetch->time = time + (*delay); //@todo ADD LATENCY HERE
             //... initialize
 
@@ -199,14 +199,14 @@ BasePrefetcher::handleMiss(Packet * &pkt, Tick time)
             }
 
             //Check if it is already in the miss_queue
-            if (inMissQueue(prefetch->paddr, prefetch->req->asid)) {
+            if (inMissQueue(prefetch->getAddr(), prefetch->req->getAsid())) {
                 addr++;
                 delay++;
                 continue;
             }
 
             //Check if it is already in the pf buffer
-            if (inPrefetch(prefetch->paddr) != pf.end()) {
+            if (inPrefetch(prefetch->getAddr()) != pf.end()) {
                 pfBufferHit++;
                 addr++;
                 delay++;
@@ -240,7 +240,7 @@ BasePrefetcher::inPrefetch(Addr address)
     //Guaranteed to only be one match, we always check before inserting
     std::list<Packet *>::iterator iter;
     for (iter=pf.begin(); iter != pf.end(); iter++) {
-        if (((*iter)->paddr & ~(Addr)(blkSize-1)) == address) {
+        if (((*iter)->getAddr() & ~(Addr)(blkSize-1)) == address) {
             return iter;
         }
     }
diff --git a/src/mem/cache/prefetch/ghb_prefetcher.hh b/src/mem/cache/prefetch/ghb_prefetcher.hh
index f25ebe166..c22b763d1 100644
--- a/src/mem/cache/prefetch/ghb_prefetcher.hh
+++ b/src/mem/cache/prefetch/ghb_prefetcher.hh
@@ -78,8 +78,8 @@ class GHBPrefetcher : public Prefetcher<TagStore, Buffering>
     void calculatePrefetch(Packet * &pkt, std::list<Addr> &addresses,
                            std::list<Tick> &delays)
     {
-        Addr blkAddr = pkt->paddr & ~(Addr)(this->blkSize-1);
-        int cpuID = pkt->cpu_num;
+        Addr blkAddr = pkt->getAddr() & ~(Addr)(this->blkSize-1);
+        int cpuID = pkt->req->getCpuNum();
         if (!useCPUId) cpuID = 0;
 
 
diff --git a/src/mem/cache/prefetch/stride_prefetcher.hh b/src/mem/cache/prefetch/stride_prefetcher.hh
index f89776215..4a8ee7de4 100644
--- a/src/mem/cache/prefetch/stride_prefetcher.hh
+++ b/src/mem/cache/prefetch/stride_prefetcher.hh
@@ -96,7 +96,7 @@ class StridePrefetcher : public Prefetcher<TagStore, Buffering>
                            std::list<Tick> &delays)
     {
 //	Addr blkAddr = pkt->paddr & ~(Addr)(this->blkSize-1);
-        int cpuID = pkt->cpu_num;
+        int cpuID = pkt->req->getCpuNum();
         if (!useCPUId) cpuID = 0;
 
         /* Scan Table for IAddr Match */
diff --git a/src/mem/cache/prefetch/tagged_prefetcher_impl.hh b/src/mem/cache/prefetch/tagged_prefetcher_impl.hh
index 9e46ba893..db5c94820 100644
--- a/src/mem/cache/prefetch/tagged_prefetcher_impl.hh
+++ b/src/mem/cache/prefetch/tagged_prefetcher_impl.hh
@@ -52,7 +52,7 @@ TaggedPrefetcher<TagStore, Buffering>::
 calculatePrefetch(Packet * &pkt, std::list<Addr> &addresses,
                   std::list<Tick> &delays)
 {
-    Addr blkAddr = pkt->paddr & ~(Addr)(this->blkSize-1);
+    Addr blkAddr = pkt->getAddr() & ~(Addr)(this->blkSize-1);
 
     for (int d=1; d <= degree; d++) {
         Addr newAddr = blkAddr + d*(this->blkSize);