6 files changed, 21 insertions, 29 deletions

diff --git a/src/mem/cache/prefetch/ghb_prefetcher.cc b/src/mem/cache/prefetch/ghb_prefetcher.cc
index dd1b8aee4..a6c419113 100644
--- a/src/mem/cache/prefetch/ghb_prefetcher.cc
+++ b/src/mem/cache/prefetch/ghb_prefetcher.cc
@@ -38,15 +38,11 @@
 
 #include "mem/cache/tags/lru.hh"
 
-#include "mem/cache/miss/miss_queue.hh"
-#include "mem/cache/miss/blocking_buffer.hh"
-
 #include "mem/cache/prefetch/ghb_prefetcher.hh"
 
 // Template Instantiations
 #ifndef DOXYGEN_SHOULD_SKIP_THIS
 
-template class GHBPrefetcher<CacheTags<LRU>, MissQueue>;
-template class GHBPrefetcher<CacheTags<LRU>, BlockingBuffer>;
+template class GHBPrefetcher<CacheTags<LRU> >;
 
 #endif //DOXYGEN_SHOULD_SKIP_THIS
diff --git a/src/mem/cache/prefetch/ghb_prefetcher.hh b/src/mem/cache/prefetch/ghb_prefetcher.hh
index 14f5747df..c558a3e64 100644
--- a/src/mem/cache/prefetch/ghb_prefetcher.hh
+++ b/src/mem/cache/prefetch/ghb_prefetcher.hh
@@ -43,16 +43,16 @@
 /**
  * A template-policy based cache. The behavior of the cache can be altered by
  * supplying different template policies. TagStore handles all tag and data
- * storage @sa TagStore. Buffering handles all misses and writes/writebacks
+ * storage @sa TagStore. MissBuffer handles all misses and writes/writebacks
  * @sa MissQueue. Coherence handles all coherence policy details @sa
  * UniCoherence, SimpleMultiCoherence.
  */
-template <class TagStore, class Buffering>
-class GHBPrefetcher : public Prefetcher<TagStore, Buffering>
+template <class TagStore>
+class GHBPrefetcher : public Prefetcher<TagStore>
 {
   protected:
 
-    Buffering* mq;
+    MissBuffer* mq;
     TagStore* tags;
 
     Addr second_last_miss_addr[64/*MAX_CPUS*/];
@@ -67,7 +67,7 @@ class GHBPrefetcher : public Prefetcher<TagStore, Buffering>
     GHBPrefetcher(int size, bool pageStop, bool serialSquash,
                   bool cacheCheckPush, bool onlyData,
                   Tick latency, int degree, bool useCPUId)
-        :Prefetcher<TagStore, Buffering>(size, pageStop, serialSquash,
+        :Prefetcher<TagStore>(size, pageStop, serialSquash,
                                          cacheCheckPush, onlyData),
          latency(latency), degree(degree), useCPUId(useCPUId)
     {
diff --git a/src/mem/cache/prefetch/stride_prefetcher.cc b/src/mem/cache/prefetch/stride_prefetcher.cc
index c3b428dab..2204871cc 100644
--- a/src/mem/cache/prefetch/stride_prefetcher.cc
+++ b/src/mem/cache/prefetch/stride_prefetcher.cc
@@ -38,15 +38,11 @@
 
 #include "mem/cache/tags/lru.hh"
 
-#include "mem/cache/miss/miss_queue.hh"
-#include "mem/cache/miss/blocking_buffer.hh"
-
 #include "mem/cache/prefetch/stride_prefetcher.hh"
 
 // Template Instantiations
 #ifndef DOXYGEN_SHOULD_SKIP_THIS
 
-template class StridePrefetcher<CacheTags<LRU>, MissQueue>;
-template class StridePrefetcher<CacheTags<LRU>, BlockingBuffer>;
+template class StridePrefetcher<CacheTags<LRU> >;
 
 #endif //DOXYGEN_SHOULD_SKIP_THIS
diff --git a/src/mem/cache/prefetch/stride_prefetcher.hh b/src/mem/cache/prefetch/stride_prefetcher.hh
index d6fb8ab66..57e430400 100644
--- a/src/mem/cache/prefetch/stride_prefetcher.hh
+++ b/src/mem/cache/prefetch/stride_prefetcher.hh
@@ -43,16 +43,16 @@
 /**
  * A template-policy based cache. The behavior of the cache can be altered by
  * supplying different template policies. TagStore handles all tag and data
- * storage @sa TagStore. Buffering handles all misses and writes/writebacks
+ * storage @sa TagStore. MissBuffer handles all misses and writes/writebacks
  * @sa MissQueue. Coherence handles all coherence policy details @sa
  * UniCoherence, SimpleMultiCoherence.
  */
-template <class TagStore, class Buffering>
-class StridePrefetcher : public Prefetcher<TagStore, Buffering>
+template <class TagStore>
+class StridePrefetcher : public Prefetcher<TagStore>
 {
   protected:
 
-    Buffering* mq;
+    MissBuffer* mq;
     TagStore* tags;
 
     class strideEntry
@@ -84,7 +84,7 @@ class StridePrefetcher : public Prefetcher<TagStore, Buffering>
     StridePrefetcher(int size, bool pageStop, bool serialSquash,
                      bool cacheCheckPush, bool onlyData,
                      Tick latency, int degree, bool useCPUId)
-        :Prefetcher<TagStore, Buffering>(size, pageStop, serialSquash,
+        :Prefetcher<TagStore>(size, pageStop, serialSquash,
                                          cacheCheckPush, onlyData),
          latency(latency), degree(degree), useCPUId(useCPUId)
     {
diff --git a/src/mem/cache/prefetch/tagged_prefetcher.hh b/src/mem/cache/prefetch/tagged_prefetcher.hh
index b61e57dcc..dc2aaec50 100644
--- a/src/mem/cache/prefetch/tagged_prefetcher.hh
+++ b/src/mem/cache/prefetch/tagged_prefetcher.hh
@@ -41,16 +41,16 @@
 /**
  * A template-policy based cache. The behavior of the cache can be altered by
  * supplying different template policies. TagStore handles all tag and data
- * storage @sa TagStore. Buffering handles all misses and writes/writebacks
+ * storage @sa TagStore. MissBuffer handles all misses and writes/writebacks
  * @sa MissQueue. Coherence handles all coherence policy details @sa
  * UniCoherence, SimpleMultiCoherence.
  */
-template <class TagStore, class Buffering>
-class TaggedPrefetcher : public Prefetcher<TagStore, Buffering>
+template <class TagStore>
+class TaggedPrefetcher : public Prefetcher<TagStore>
 {
   protected:
 
-    Buffering* mq;
+    MissBuffer* mq;
     TagStore* tags;
 
     Tick latency;
diff --git a/src/mem/cache/prefetch/tagged_prefetcher_impl.hh b/src/mem/cache/prefetch/tagged_prefetcher_impl.hh
index a18de4571..b3d4284c7 100644
--- a/src/mem/cache/prefetch/tagged_prefetcher_impl.hh
+++ b/src/mem/cache/prefetch/tagged_prefetcher_impl.hh
@@ -36,20 +36,20 @@
 #include "arch/isa_traits.hh"
 #include "mem/cache/prefetch/tagged_prefetcher.hh"
 
-template <class TagStore, class Buffering>
-TaggedPrefetcher<TagStore, Buffering>::
+template <class TagStore>
+TaggedPrefetcher<TagStore>::
 TaggedPrefetcher(int size, bool pageStop, bool serialSquash,
                  bool cacheCheckPush, bool onlyData,
                  Tick latency, int degree)
-    :Prefetcher<TagStore, Buffering>(size, pageStop, serialSquash,
+    :Prefetcher<TagStore>(size, pageStop, serialSquash,
                                      cacheCheckPush, onlyData),
      latency(latency), degree(degree)
 {
 }
 
-template <class TagStore, class Buffering>
+template <class TagStore>
 void
-TaggedPrefetcher<TagStore, Buffering>::
+TaggedPrefetcher<TagStore>::
 calculatePrefetch(PacketPtr &pkt, std::list<Addr> &addresses,
                   std::list<Tick> &delays)
 {