diff options
Diffstat (limited to 'src/mem/cache/prefetch')
| -rw-r--r-- | src/mem/cache/prefetch/Prefetcher.py | 35 | ||||
| -rw-r--r-- | src/mem/cache/prefetch/SConscript | 1 | ||||
| -rw-r--r-- | src/mem/cache/prefetch/base.cc | 31 | ||||
| -rw-r--r-- | src/mem/cache/prefetch/base.hh | 30 | ||||
| -rw-r--r-- | src/mem/cache/prefetch/ghb.cc | 7 | ||||
| -rw-r--r-- | src/mem/cache/prefetch/ghb.hh | 11 | ||||
| -rw-r--r-- | src/mem/cache/prefetch/stride.cc | 7 | ||||
| -rw-r--r-- | src/mem/cache/prefetch/stride.hh | 9 | ||||
| -rw-r--r-- | src/mem/cache/prefetch/tagged.cc | 10 | ||||
| -rw-r--r-- | src/mem/cache/prefetch/tagged.hh | 9 |
10 files changed, 102 insertions, 48 deletions
diff --git a/src/mem/cache/prefetch/Prefetcher.py b/src/mem/cache/prefetch/Prefetcher.py new file mode 100644 index 000000000..c2c17fa96 --- /dev/null +++ b/src/mem/cache/prefetch/Prefetcher.py @@ -0,0 +1,35 @@ +from m5.SimObject import SimObject +from m5.params import * +class BasePrefetcher(SimObject): + type = 'BasePrefetcher' + abstract = True + size = Param.Int(100, + "Number of entries in the hardware prefetch queue") + cross_pages = Param.Bool(False, + "Allow prefetches to cross virtual page boundaries") + serial_squash = Param.Bool(False, + "Squash prefetches with a later time on a subsequent miss") + degree = Param.Int(1, + "Degree of the prefetch depth") + latency = Param.Latency('10t', + "Latency of the prefetcher") + use_cpu_id = Param.Bool(True, + "Use the CPU ID to separate calculations of prefetches") + data_accesses_only = Param.Bool(False, + "Only prefetch on data not on instruction accesses") + +class GHBPrefetcher(BasePrefetcher): + type = 'GHBPrefetcher' + cxx_class = 'GHBPrefetcher' + +class StridePrefetcher(BasePrefetcher): + type = 'StridePrefetcher' + cxx_class = 'StridePrefetcher' + +class TaggedPrefetcher(BasePrefetcher): + type = 'TaggedPrefetcher' + cxx_class = 'TaggedPrefetcher' + + + + diff --git a/src/mem/cache/prefetch/SConscript b/src/mem/cache/prefetch/SConscript index 9d05a8ee4..2310940c1 100644 --- a/src/mem/cache/prefetch/SConscript +++ b/src/mem/cache/prefetch/SConscript @@ -32,6 +32,7 @@ Import('*') if env['TARGET_ISA'] == 'no': Return() +SimObject('Prefetcher.py') Source('base.cc') Source('ghb.cc') diff --git a/src/mem/cache/prefetch/base.cc b/src/mem/cache/prefetch/base.cc index 0f9290186..834787db6 100644 --- a/src/mem/cache/prefetch/base.cc +++ b/src/mem/cache/prefetch/base.cc @@ -43,10 +43,10 @@ #include "mem/cache/base.hh" #include "mem/request.hh" -BasePrefetcher::BasePrefetcher(const BaseCacheParams *p) - : size(p->prefetcher_size), pageStop(!p->prefetch_past_page), - serialSquash(p->prefetch_serial_squash), - onlyData(p->prefetch_data_accesses_only) +BasePrefetcher::BasePrefetcher(const Params *p) + : SimObject(p), size(p->size), latency(p->latency), degree(p->degree), + useContextId(p->use_cpu_id), pageStop(!p->cross_pages), + serialSquash(p->serial_squash), onlyData(p->data_accesses_only) { } @@ -55,54 +55,53 @@ BasePrefetcher::setCache(BaseCache *_cache) { cache = _cache; blkSize = cache->getBlockSize(); - _name = cache->name() + "-pf"; } void -BasePrefetcher::regStats(const std::string &name) +BasePrefetcher::regStats() { pfIdentified - .name(name + ".prefetcher.num_hwpf_identified") + .name(name() + ".prefetcher.num_hwpf_identified") .desc("number of hwpf identified") ; pfMSHRHit - .name(name + ".prefetcher.num_hwpf_already_in_mshr") + .name(name() + ".prefetcher.num_hwpf_already_in_mshr") .desc("number of hwpf that were already in mshr") ; pfCacheHit - .name(name + ".prefetcher.num_hwpf_already_in_cache") + .name(name() + ".prefetcher.num_hwpf_already_in_cache") .desc("number of hwpf that were already in the cache") ; pfBufferHit - .name(name + ".prefetcher.num_hwpf_already_in_prefetcher") + .name(name() + ".prefetcher.num_hwpf_already_in_prefetcher") .desc("number of hwpf that were already in the prefetch queue") ; pfRemovedFull - .name(name + ".prefetcher.num_hwpf_evicted") + .name(name() + ".prefetcher.num_hwpf_evicted") .desc("number of hwpf removed due to no buffer left") ; pfRemovedMSHR - .name(name + ".prefetcher.num_hwpf_removed_MSHR_hit") + .name(name() + ".prefetcher.num_hwpf_removed_MSHR_hit") .desc("number of hwpf removed because MSHR allocated") ; pfIssued - .name(name + ".prefetcher.num_hwpf_issued") + .name(name() + ".prefetcher.num_hwpf_issued") .desc("number of hwpf issued") ; pfSpanPage - .name(name + ".prefetcher.num_hwpf_span_page") + .name(name() + ".prefetcher.num_hwpf_span_page") .desc("number of hwpf spanning a virtual page") ; pfSquashed - .name(name + ".prefetcher.num_hwpf_squashed_from_miss") + .name(name() + ".prefetcher.num_hwpf_squashed_from_miss") .desc("number of hwpf that got squashed due to a miss " "aborting calculation time") ; @@ -276,3 +275,5 @@ BasePrefetcher::samePage(Addr a, Addr b) { return roundDown(a, TheISA::VMPageSize) == roundDown(b, TheISA::VMPageSize); } + + diff --git a/src/mem/cache/prefetch/base.hh b/src/mem/cache/prefetch/base.hh index e3c0cbf16..ead163215 100644 --- a/src/mem/cache/prefetch/base.hh +++ b/src/mem/cache/prefetch/base.hh @@ -41,10 +41,11 @@ #include "base/statistics.hh" #include "mem/packet.hh" #include "params/BaseCache.hh" +#include "sim/sim_object.hh" class BaseCache; -class BasePrefetcher +class BasePrefetcher : public SimObject { protected: @@ -62,6 +63,14 @@ class BasePrefetcher /** The block size of the parent cache. */ int blkSize; + /** The latency before a prefetch is issued */ + Tick latency; + + /** The number of prefetches to issue */ + unsigned degree; + + /** If patterns should be found per context id */ + bool useContextId; /** Do we prefetch across page boundaries. */ bool pageStop; @@ -71,8 +80,6 @@ class BasePrefetcher /** Do we prefetch on only data reads, or on inst reads as well. */ bool onlyData; - std::string _name; - public: Stats::Scalar pfIdentified; @@ -85,16 +92,14 @@ class BasePrefetcher Stats::Scalar pfSpanPage; Stats::Scalar pfSquashed; - void regStats(const std::string &name); + void regStats(); public: - - BasePrefetcher(const BaseCacheParams *p); + typedef BasePrefetcherParams Params; + BasePrefetcher(const Params *p); virtual ~BasePrefetcher() {} - const std::string name() const { return _name; } - void setCache(BaseCache *_cache); /** @@ -130,7 +135,12 @@ class BasePrefetcher * Utility function: are addresses a and b on the same VM page? */ bool samePage(Addr a, Addr b); -}; - + public: + const Params* + params() const + { + return dynamic_cast<const Params *>(_params); + } +}; #endif //__MEM_CACHE_PREFETCH_BASE_PREFETCHER_HH__ diff --git a/src/mem/cache/prefetch/ghb.cc b/src/mem/cache/prefetch/ghb.cc index dbc565bfd..b9fc8e675 100644 --- a/src/mem/cache/prefetch/ghb.cc +++ b/src/mem/cache/prefetch/ghb.cc @@ -71,3 +71,10 @@ GHBPrefetcher::calculatePrefetch(PacketPtr &pkt, std::list<Addr> &addresses, } } } + + +GHBPrefetcher* +GHBPrefetcherParams::create() +{ + return new GHBPrefetcher(this); +} diff --git a/src/mem/cache/prefetch/ghb.hh b/src/mem/cache/prefetch/ghb.hh index c85221a39..a21b57b93 100644 --- a/src/mem/cache/prefetch/ghb.hh +++ b/src/mem/cache/prefetch/ghb.hh @@ -37,6 +37,7 @@ #define __MEM_CACHE_PREFETCH_GHB_PREFETCHER_HH__ #include "mem/cache/prefetch/base.hh" +#include "params/GHBPrefetcher.hh" class GHBPrefetcher : public BasePrefetcher { @@ -47,15 +48,9 @@ class GHBPrefetcher : public BasePrefetcher Addr secondLastMissAddr[Max_Contexts]; Addr lastMissAddr[Max_Contexts]; - Tick latency; - int degree; - bool useContextId; - public: - - GHBPrefetcher(const BaseCacheParams *p) - : BasePrefetcher(p), latency(p->prefetch_latency), - degree(p->prefetch_degree), useContextId(p->prefetch_use_cpu_id) + GHBPrefetcher(const Params *p) + : BasePrefetcher(p) { } diff --git a/src/mem/cache/prefetch/stride.cc b/src/mem/cache/prefetch/stride.cc index a5cc805ef..645bc5fc5 100644 --- a/src/mem/cache/prefetch/stride.cc +++ b/src/mem/cache/prefetch/stride.cc @@ -132,3 +132,10 @@ StridePrefetcher::calculatePrefetch(PacketPtr &pkt, std::list<Addr> &addresses, tab.push_back(new_entry); } } + + +StridePrefetcher* +StridePrefetcherParams::create() +{ + return new StridePrefetcher(this); +} diff --git a/src/mem/cache/prefetch/stride.hh b/src/mem/cache/prefetch/stride.hh index c78739b4e..51b4252a1 100644 --- a/src/mem/cache/prefetch/stride.hh +++ b/src/mem/cache/prefetch/stride.hh @@ -39,6 +39,7 @@ #include <climits> #include "mem/cache/prefetch/base.hh" +#include "params/StridePrefetcher.hh" class StridePrefetcher : public BasePrefetcher { @@ -63,15 +64,11 @@ class StridePrefetcher : public BasePrefetcher Addr *lastMissAddr[Max_Contexts]; std::list<StrideEntry*> table[Max_Contexts]; - Tick latency; - int degree; - bool useContextId; public: - StridePrefetcher(const BaseCacheParams *p) - : BasePrefetcher(p), latency(p->prefetch_latency), - degree(p->prefetch_degree), useContextId(p->prefetch_use_cpu_id) + StridePrefetcher(const Params *p) + : BasePrefetcher(p) { } diff --git a/src/mem/cache/prefetch/tagged.cc b/src/mem/cache/prefetch/tagged.cc index 700af3790..c875b586b 100644 --- a/src/mem/cache/prefetch/tagged.cc +++ b/src/mem/cache/prefetch/tagged.cc @@ -35,9 +35,8 @@ #include "mem/cache/prefetch/tagged.hh" -TaggedPrefetcher::TaggedPrefetcher(const BaseCacheParams *p) - : BasePrefetcher(p), - latency(p->prefetch_latency), degree(p->prefetch_degree) +TaggedPrefetcher::TaggedPrefetcher(const Params *p) + : BasePrefetcher(p) { } @@ -62,3 +61,8 @@ calculatePrefetch(PacketPtr &pkt, std::list<Addr> &addresses, } +TaggedPrefetcher* +TaggedPrefetcherParams::create() +{ + return new TaggedPrefetcher(this); +} diff --git a/src/mem/cache/prefetch/tagged.hh b/src/mem/cache/prefetch/tagged.hh index 78e20083d..8037196f8 100644 --- a/src/mem/cache/prefetch/tagged.hh +++ b/src/mem/cache/prefetch/tagged.hh @@ -37,17 +37,14 @@ #define __MEM_CACHE_PREFETCH_TAGGED_PREFETCHER_HH__ #include "mem/cache/prefetch/base.hh" +#include "params/TaggedPrefetcher.hh" + class TaggedPrefetcher : public BasePrefetcher { - protected: - - Tick latency; - int degree; - public: - TaggedPrefetcher(const BaseCacheParams *p); + TaggedPrefetcher(const Params *p); ~TaggedPrefetcher() {} |