summaryrefslogtreecommitdiff
path: root/src/mem/cache/prefetch
diff options
context:
space:
mode:
Diffstat (limited to 'src/mem/cache/prefetch')
-rw-r--r--src/mem/cache/prefetch/Prefetcher.py2
-rw-r--r--src/mem/cache/prefetch/base.cc9
-rw-r--r--src/mem/cache/prefetch/base.hh4
3 files changed, 8 insertions, 7 deletions
diff --git a/src/mem/cache/prefetch/Prefetcher.py b/src/mem/cache/prefetch/Prefetcher.py
index 6bb4e52d3..fed59661d 100644
--- a/src/mem/cache/prefetch/Prefetcher.py
+++ b/src/mem/cache/prefetch/Prefetcher.py
@@ -67,7 +67,7 @@ class BasePrefetcher(ClockedObject):
"Let lower cache prefetcher train on prefetch requests")
inst_tagged = Param.Bool(True,
"Perform a tagged prefetch for instruction fetches always")
- sys = Param.System(Parent.any, "System this device belongs to")
+ sys = Param.System(Parent.any, "System this prefetcher belongs to")
class StridePrefetcher(BasePrefetcher):
type = 'StridePrefetcher'
diff --git a/src/mem/cache/prefetch/base.cc b/src/mem/cache/prefetch/base.cc
index 971ecf5b0..ab740461d 100644
--- a/src/mem/cache/prefetch/base.cc
+++ b/src/mem/cache/prefetch/base.cc
@@ -47,9 +47,7 @@
#include <list>
-#include "arch/isa_traits.hh"
#include "base/trace.hh"
-#include "config/the_isa.hh"
#include "debug/HWPrefetch.hh"
#include "mem/cache/prefetch/base.hh"
#include "mem/cache/base.hh"
@@ -63,7 +61,8 @@ BasePrefetcher::BasePrefetcher(const Params *p)
serialSquash(p->serial_squash), onlyData(p->data_accesses_only),
onMissOnly(p->on_miss_only), onReadOnly(p->on_read_only),
onPrefetch(p->on_prefetch), system(p->sys),
- masterId(system->getMasterId(name()))
+ masterId(system->getMasterId(name())),
+ pageBytes(system->getPageBytes())
{
}
@@ -312,9 +311,9 @@ BasePrefetcher::inPrefetch(Addr address, bool is_secure)
}
bool
-BasePrefetcher::samePage(Addr a, Addr b)
+BasePrefetcher::samePage(Addr a, Addr b) const
{
- return roundDown(a, TheISA::PageBytes) == roundDown(b, TheISA::PageBytes);
+ return roundDown(a, pageBytes) == roundDown(b, pageBytes);
}
diff --git a/src/mem/cache/prefetch/base.hh b/src/mem/cache/prefetch/base.hh
index 22a4c68f6..54f91a509 100644
--- a/src/mem/cache/prefetch/base.hh
+++ b/src/mem/cache/prefetch/base.hh
@@ -118,6 +118,8 @@ class BasePrefetcher : public ClockedObject
/** Request id for prefetches */
MasterID masterId;
+ const Addr pageBytes;
+
public:
Stats::Scalar pfIdentified;
@@ -172,7 +174,7 @@ class BasePrefetcher : public ClockedObject
/**
* Utility function: are addresses a and b on the same VM page?
*/
- bool samePage(Addr a, Addr b);
+ bool samePage(Addr a, Addr b) const;
public:
const Params*
params() const