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Diffstat (limited to 'src/mem/cache/tags/Tags.py')
-rw-r--r-- | src/mem/cache/tags/Tags.py | 18 |
1 files changed, 14 insertions, 4 deletions
diff --git a/src/mem/cache/tags/Tags.py b/src/mem/cache/tags/Tags.py index 7c0dded32..ab1282ac9 100644 --- a/src/mem/cache/tags/Tags.py +++ b/src/mem/cache/tags/Tags.py @@ -53,14 +53,24 @@ class BaseTags(ClockedObject): hit_latency = Param.Cycles(Parent.hit_latency, "The hit latency for this cache") -class LRU(BaseTags): - type = 'LRU' - cxx_class = 'LRU' - cxx_header = "mem/cache/tags/lru.hh" +class BaseSetAssoc(BaseTags): + type = 'BaseSetAssoc' + abstract = True + cxx_header = "mem/cache/tags/base_set_assoc.hh" assoc = Param.Int(Parent.assoc, "associativity") sequential_access = Param.Bool(Parent.sequential_access, "Whether to access tags and data sequentially") +class LRU(BaseSetAssoc): + type = 'LRU' + cxx_class = 'LRU' + cxx_header = "mem/cache/tags/lru.hh" + +class RandomRepl(BaseSetAssoc): + type = 'RandomRepl' + cxx_class = 'RandomRepl' + cxx_header = "mem/cache/tags/random_repl.hh" + class FALRU(BaseTags): type = 'FALRU' cxx_class = 'FALRU' |