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-rw-r--r--src/mem/cache/tags/Tags.py15
1 files changed, 10 insertions, 5 deletions
diff --git a/src/mem/cache/tags/Tags.py b/src/mem/cache/tags/Tags.py
index ab1282ac9..6c0b85044 100644
--- a/src/mem/cache/tags/Tags.py
+++ b/src/mem/cache/tags/Tags.py
@@ -49,17 +49,22 @@ class BaseTags(ClockedObject):
# Get the block size from the parent (system)
block_size = Param.Int(Parent.cache_line_size, "block size in bytes")
- # Get the hit latency from the parent (cache)
- hit_latency = Param.Cycles(Parent.hit_latency,
- "The hit latency for this cache")
+ # Get the tag lookup latency from the parent (cache)
+ tag_latency = Param.Cycles(Parent.tag_latency,
+ "The tag lookup latency for this cache")
+
+ # Get the RAM access latency from the parent (cache)
+ data_latency = Param.Cycles(Parent.data_latency,
+ "The data access latency for this cache")
+
+ sequential_access = Param.Bool(Parent.sequential_access,
+ "Whether to access tags and data sequentially")
class BaseSetAssoc(BaseTags):
type = 'BaseSetAssoc'
abstract = True
cxx_header = "mem/cache/tags/base_set_assoc.hh"
assoc = Param.Int(Parent.assoc, "associativity")
- sequential_access = Param.Bool(Parent.sequential_access,
- "Whether to access tags and data sequentially")
class LRU(BaseSetAssoc):
type = 'LRU'