6 files changed, 24 insertions, 25 deletions

diff --git a/src/mem/cache/tags/fa_lru.cc b/src/mem/cache/tags/fa_lru.cc
index cc2f12eef..1a607dc80 100644
--- a/src/mem/cache/tags/fa_lru.cc
+++ b/src/mem/cache/tags/fa_lru.cc
@@ -42,7 +42,7 @@
 
 using namespace std;
 
-FALRU::FALRU(unsigned _blkSize, unsigned _size, unsigned hit_latency)
+FALRU::FALRU(unsigned _blkSize, unsigned _size, Cycles hit_latency)
     : blkSize(_blkSize), size(_size), hitLatency(hit_latency)
 {
     if (!isPowerOf2(blkSize))
@@ -159,7 +159,7 @@ FALRU::invalidate(FALRU::BlkType *blk)
 }
 
 FALRUBlk*
-FALRU::accessBlock(Addr addr, int &lat, int context_src, int *inCache)
+FALRU::accessBlock(Addr addr, Cycles &lat, int context_src, int *inCache)
 {
     accesses++;
     int tmp_in_cache = 0;
diff --git a/src/mem/cache/tags/fa_lru.hh b/src/mem/cache/tags/fa_lru.hh
index 66f70a89b..19e21688c 100644
--- a/src/mem/cache/tags/fa_lru.hh
+++ b/src/mem/cache/tags/fa_lru.hh
@@ -85,7 +85,7 @@ class FALRU : public BaseTags
     /** The size of the cache. */
     const unsigned size;
     /** The hit latency of the cache. */
-    const unsigned hitLatency;
+    const Cycles hitLatency;
 
     /** Array of pointers to blocks at the cache size  boundaries. */
     FALRUBlk **cacheBoundaries;
@@ -155,7 +155,7 @@ public:
      * @param size The size of the cache.
      * @param hit_latency The hit latency of the cache.
      */
-    FALRU(unsigned blkSize, unsigned size, unsigned hit_latency);
+    FALRU(unsigned blkSize, unsigned size, Cycles hit_latency);
     ~FALRU();
 
     /**
@@ -181,7 +181,7 @@ public:
      * @param inCache The FALRUBlk::inCache flags.
      * @return Pointer to the cache block.
      */
-    FALRUBlk* accessBlock(Addr addr, int &lat, int context_src, int *inCache = 0);
+    FALRUBlk* accessBlock(Addr addr, Cycles &lat, int context_src, int *inCache = 0);
 
     /**
      * Find the block in the cache, do not update the replacement data.
@@ -205,7 +205,7 @@ public:
      * Return the hit latency of this cache.
      * @return The hit latency.
      */
-    int getHitLatency() const
+    Cycles getHitLatency() const
     {
         return hitLatency;
     }
diff --git a/src/mem/cache/tags/iic.cc b/src/mem/cache/tags/iic.cc
index 45807ef28..b9e582c29 100644
--- a/src/mem/cache/tags/iic.cc
+++ b/src/mem/cache/tags/iic.cc
@@ -220,11 +220,11 @@ IIC::regStats(const string &name)
 
 
 IICTag*
-IIC::accessBlock(Addr addr, int &lat, int context_src)
+IIC::accessBlock(Addr addr, Cycles &lat, int context_src)
 {
     Addr tag = extractTag(addr);
     unsigned set = hash(addr);
-    int set_lat;
+    Cycles set_lat;
 
     unsigned long chain_ptr = tagNull;
 
@@ -232,11 +232,11 @@ IIC::accessBlock(Addr addr, int &lat, int context_src)
         setAccess.sample(set);
 
     IICTag *tag_ptr = sets[set].findTag(tag, chain_ptr);
-    set_lat = 1;
+    set_lat = Cycles(1);
     if (tag_ptr == NULL && chain_ptr != tagNull) {
         int secondary_depth;
         tag_ptr = secondaryChain(tag, chain_ptr, &secondary_depth);
-        set_lat += secondary_depth;
+        set_lat += Cycles(secondary_depth);
         // set depth for statistics fix this later!!! egh
         sets[set].depth = set_lat;
 
@@ -250,9 +250,7 @@ IIC::accessBlock(Addr addr, int &lat, int context_src)
         }
 
     }
-    // @todo: is hashDelay is really cycles, then
-    // multiply with period
-    set_lat = set_lat * hashDelay + hitLatency;
+    set_lat = Cycles(set_lat * hashDelay + hitLatency);
     if (tag_ptr != NULL) {
         // IIC replacement: if this is not the first element of
         //   list, reorder
@@ -263,8 +261,9 @@ IIC::accessBlock(Addr addr, int &lat, int context_src)
         hitDepthTotal += sets[set].depth;
         tag_ptr->status |= BlkReferenced;
         lat = set_lat;
-        if (tag_ptr->whenReady > curTick() && tag_ptr->whenReady - curTick() > set_lat) {
-            lat = tag_ptr->whenReady - curTick();
+        if (tag_ptr->whenReady > curTick() &&
+            cache->ticksToCycles(tag_ptr->whenReady - curTick()) > set_lat) {
+            lat = cache->ticksToCycles(tag_ptr->whenReady - curTick());
         }
 
         tag_ptr->refCount += 1;
diff --git a/src/mem/cache/tags/iic.hh b/src/mem/cache/tags/iic.hh
index 97011d1c5..91e947704 100644
--- a/src/mem/cache/tags/iic.hh
+++ b/src/mem/cache/tags/iic.hh
@@ -176,7 +176,7 @@ class IIC : public BaseTags
     /** The associativity of the primary table. */
     const unsigned assoc;
     /** The base hit latency. */
-    const unsigned hitLatency;
+    const Cycles hitLatency;
     /** The subblock size, used for compression. */
     const unsigned subSize;
 
@@ -278,9 +278,9 @@ class IIC : public BaseTags
         /** The associativity of the primary table. */
         unsigned assoc;
         /** The number of cycles for each hash lookup. */
-        unsigned hashDelay;
+        Cycles hashDelay;
         /** The number of cycles to read the data. */
-        unsigned hitLatency;
+        Cycles hitLatency;
         /** The replacement policy. */
         Repl *rp;
         /** The subblock size in bytes. */
@@ -420,7 +420,7 @@ class IIC : public BaseTags
      * @param lat The access latency.
      * @return A pointer to the block found, if any.
      */
-    IICTag* accessBlock(Addr addr, int &lat, int context_src);
+    IICTag* accessBlock(Addr addr, Cycles &lat, int context_src);
 
     /**
      * Find the block, do not update the replacement data.
diff --git a/src/mem/cache/tags/lru.cc b/src/mem/cache/tags/lru.cc
index 8d32d4b35..00b13e2d8 100644
--- a/src/mem/cache/tags/lru.cc
+++ b/src/mem/cache/tags/lru.cc
@@ -116,7 +116,7 @@ LRU::~LRU()
 }
 
 LRU::BlkType*
-LRU::accessBlock(Addr addr, int &lat, int master_id)
+LRU::accessBlock(Addr addr, Cycles &lat, int master_id)
 {
     Addr tag = extractTag(addr);
     unsigned set = extractSet(addr);
@@ -128,8 +128,8 @@ LRU::accessBlock(Addr addr, int &lat, int master_id)
         DPRINTF(CacheRepl, "set %x: moving blk %x to MRU\n",
                 set, regenerateBlkAddr(tag, set));
         if (blk->whenReady > curTick()
-            && blk->whenReady - curTick() > hitLatency) {
-            lat = blk->whenReady - curTick();
+            && cache->ticksToCycles(blk->whenReady - curTick()) > hitLatency) {
+            lat = cache->ticksToCycles(blk->whenReady - curTick());
         }
         blk->refCount += 1;
     }
diff --git a/src/mem/cache/tags/lru.hh b/src/mem/cache/tags/lru.hh
index 7938fcc3c..427dba667 100644
--- a/src/mem/cache/tags/lru.hh
+++ b/src/mem/cache/tags/lru.hh
@@ -68,7 +68,7 @@ class LRU : public BaseTags
     /** The associativity of the cache. */
     const unsigned assoc;
     /** The hit latency. */
-    const unsigned hitLatency;
+    const Cycles hitLatency;
 
     /** The cache sets. */
     CacheSet *sets;
@@ -139,7 +139,7 @@ public:
      * @param lat The access latency.
      * @return Pointer to the cache block if found.
      */
-    BlkType* accessBlock(Addr addr, int &lat, int context_src);
+    BlkType* accessBlock(Addr addr, Cycles &lat, int context_src);
 
     /**
      * Finds the given address in the cache, do not update replacement data.
@@ -221,7 +221,7 @@ public:
      * Return the hit latency.
      * @return the hit latency.
      */
-    int getHitLatency() const
+    Cycles getHitLatency() const
     {
         return hitLatency;
     }