diff options
Diffstat (limited to 'src/mem/cache/tags')
-rw-r--r-- | src/mem/cache/tags/Tags.py | 4 | ||||
-rw-r--r-- | src/mem/cache/tags/base.cc | 6 | ||||
-rw-r--r-- | src/mem/cache/tags/base.hh | 18 | ||||
-rw-r--r-- | src/mem/cache/tags/base_set_assoc.hh | 27 | ||||
-rw-r--r-- | src/mem/cache/tags/fa_lru.cc | 18 | ||||
-rw-r--r-- | src/mem/cache/tags/fa_lru.hh | 5 | ||||
-rw-r--r-- | src/mem/cache/tags/sector_tags.cc | 18 | ||||
-rw-r--r-- | src/mem/cache/tags/sector_tags.hh | 4 |
8 files changed, 36 insertions, 64 deletions
diff --git a/src/mem/cache/tags/Tags.py b/src/mem/cache/tags/Tags.py index 8e302898c..b34779eef 100644 --- a/src/mem/cache/tags/Tags.py +++ b/src/mem/cache/tags/Tags.py @@ -54,10 +54,6 @@ class BaseTags(ClockedObject): tag_latency = Param.Cycles(Parent.tag_latency, "The tag lookup latency for this cache") - # Get the RAM access latency from the parent (cache) - data_latency = Param.Cycles(Parent.data_latency, - "The data access latency for this cache") - # Get the warmup percentage from the parent (cache) warmup_percentage = Param.Percent(Parent.warmup_percentage, "Percentage of tags to be touched to warm up the cache") diff --git a/src/mem/cache/tags/base.cc b/src/mem/cache/tags/base.cc index c6a9a8295..5fbbdc194 100644 --- a/src/mem/cache/tags/base.cc +++ b/src/mem/cache/tags/base.cc @@ -61,11 +61,7 @@ BaseTags::BaseTags(const Params *p) : ClockedObject(p), blkSize(p->block_size), blkMask(blkSize - 1), - size(p->size), - lookupLatency(p->tag_latency), - accessLatency(p->sequential_access ? - p->tag_latency + p->data_latency : - std::max(p->tag_latency, p->data_latency)), + size(p->size), lookupLatency(p->tag_latency), cache(nullptr), indexingPolicy(p->indexing_policy), warmupBound((p->warmup_percentage/100.0) * (p->size / p->block_size)), warmedUp(false), numBlocks(p->size / p->block_size), diff --git a/src/mem/cache/tags/base.hh b/src/mem/cache/tags/base.hh index a7a35ffbb..273abf5dc 100644 --- a/src/mem/cache/tags/base.hh +++ b/src/mem/cache/tags/base.hh @@ -79,12 +79,7 @@ class BaseTags : public ClockedObject const unsigned size; /** The tag lookup latency of the cache. */ const Cycles lookupLatency; - /** - * The total access latency of the cache. This latency - * is different depending on the cache access mode - * (parallel or sequential) - */ - const Cycles accessLatency; + /** Pointer to the parent cache. */ BaseCache *cache; @@ -293,6 +288,17 @@ class BaseTags : public ClockedObject virtual CacheBlk* findVictim(Addr addr, const bool is_secure, std::vector<CacheBlk*>& evict_blks) const = 0; + /** + * Access block and update replacement data. May not succeed, in which case + * nullptr is returned. This has all the implications of a cache access and + * should only be used as such. Returns the tag lookup latency as a side + * effect. + * + * @param addr The address to find. + * @param is_secure True if the target memory space is secure. + * @param lat The latency of the tag lookup. + * @return Pointer to the cache block if found. + */ virtual CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles &lat) = 0; /** diff --git a/src/mem/cache/tags/base_set_assoc.hh b/src/mem/cache/tags/base_set_assoc.hh index 58aceb087..bc98afa5e 100644 --- a/src/mem/cache/tags/base_set_assoc.hh +++ b/src/mem/cache/tags/base_set_assoc.hh @@ -115,12 +115,13 @@ class BaseSetAssoc : public BaseTags /** * Access block and update replacement data. May not succeed, in which case - * nullptr is returned. This has all the implications of a cache - * access and should only be used as such. Returns the access latency as a - * side effect. + * nullptr is returned. This has all the implications of a cache access and + * should only be used as such. Returns the tag lookup latency as a side + * effect. + * * @param addr The address to find. * @param is_secure True if the target memory space is secure. - * @param lat The access latency. + * @param lat The latency of the tag lookup. * @return Pointer to the cache block if found. */ CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles &lat) override @@ -139,28 +140,18 @@ class BaseSetAssoc : public BaseTags dataAccesses += allocAssoc; } + // If a cache hit if (blk != nullptr) { - // If a cache hit - lat = accessLatency; - // Check if the block to be accessed is available. If not, - // apply the accessLatency on top of block->whenReady. - if (blk->whenReady > curTick() && - cache->ticksToCycles(blk->whenReady - curTick()) > - accessLatency) { - lat = cache->ticksToCycles(blk->whenReady - curTick()) + - accessLatency; - } - // Update number of references to accessed block blk->refCount++; // Update replacement data of accessed block replacementPolicy->touch(blk->replacementData); - } else { - // If a cache miss - lat = lookupLatency; } + // The tag lookup latency is the same for a hit or a miss + lat = lookupLatency; + return blk; } diff --git a/src/mem/cache/tags/fa_lru.cc b/src/mem/cache/tags/fa_lru.cc index 2c92a940f..964846871 100644 --- a/src/mem/cache/tags/fa_lru.cc +++ b/src/mem/cache/tags/fa_lru.cc @@ -153,30 +153,22 @@ FALRU::accessBlock(Addr addr, bool is_secure, Cycles &lat, CachesMask mask = 0; FALRUBlk* blk = static_cast<FALRUBlk*>(findBlock(addr, is_secure)); + // If a cache hit if (blk && blk->isValid()) { - // If a cache hit - lat = accessLatency; - // Check if the block to be accessed is available. If not, - // apply the accessLatency on top of block->whenReady. - if (blk->whenReady > curTick() && - cache->ticksToCycles(blk->whenReady - curTick()) > - accessLatency) { - lat = cache->ticksToCycles(blk->whenReady - curTick()) + - accessLatency; - } mask = blk->inCachesMask; moveToHead(blk); - } else { - // If a cache miss - lat = lookupLatency; } + if (in_caches_mask) { *in_caches_mask = mask; } cacheTracking.recordAccess(blk); + // The tag lookup latency is the same for a hit or a miss + lat = lookupLatency; + return blk; } diff --git a/src/mem/cache/tags/fa_lru.hh b/src/mem/cache/tags/fa_lru.hh index 6ea4c8d6a..1de6de400 100644 --- a/src/mem/cache/tags/fa_lru.hh +++ b/src/mem/cache/tags/fa_lru.hh @@ -180,10 +180,11 @@ class FALRU : public BaseTags * Access block and update replacement data. May not succeed, in which * case nullptr pointer is returned. This has all the implications of a * cache access and should only be used as such. - * Returns the access latency and inCachesMask flags as a side effect. + * Returns tag lookup latency and the inCachesMask flags as a side effect. + * * @param addr The address to look for. * @param is_secure True if the target memory space is secure. - * @param lat The latency of the access. + * @param lat The latency of the tag lookup. * @param in_cache_mask Mask indicating the caches in which the blk fits. * @return Pointer to the cache block. */ diff --git a/src/mem/cache/tags/sector_tags.cc b/src/mem/cache/tags/sector_tags.cc index 24751c97d..02649cc40 100644 --- a/src/mem/cache/tags/sector_tags.cc +++ b/src/mem/cache/tags/sector_tags.cc @@ -149,18 +149,8 @@ SectorTags::accessBlock(Addr addr, bool is_secure, Cycles &lat) dataAccesses += allocAssoc*numBlocksPerSector; } + // If a cache hit if (blk != nullptr) { - // If a cache hit - lat = accessLatency; - // Check if the block to be accessed is available. If not, - // apply the accessLatency on top of block->whenReady. - if (blk->whenReady > curTick() && - cache->ticksToCycles(blk->whenReady - curTick()) > - accessLatency) { - lat = cache->ticksToCycles(blk->whenReady - curTick()) + - accessLatency; - } - // Update number of references to accessed block blk->refCount++; @@ -171,11 +161,11 @@ SectorTags::accessBlock(Addr addr, bool is_secure, Cycles &lat) // Update replacement data of accessed block, which is shared with // the whole sector it belongs to replacementPolicy->touch(sector_blk->replacementData); - } else { - // If a cache miss - lat = lookupLatency; } + // The tag lookup latency is the same for a hit or a miss + lat = lookupLatency; + return blk; } diff --git a/src/mem/cache/tags/sector_tags.hh b/src/mem/cache/tags/sector_tags.hh index 1149ba1e0..f9d47f3c4 100644 --- a/src/mem/cache/tags/sector_tags.hh +++ b/src/mem/cache/tags/sector_tags.hh @@ -118,12 +118,12 @@ class SectorTags : public BaseTags /** * Access block and update replacement data. May not succeed, in which * case nullptr is returned. This has all the implications of a cache - * access and should only be used as such. Returns the access latency + * access and should only be used as such. Returns the tag lookup latency * as a side effect. * * @param addr The address to find. * @param is_secure True if the target memory space is secure. - * @param lat The access latency. + * @param lat The latency of the tag lookup. * @return Pointer to the cache block if found. */ CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles &lat) override; |