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-rw-r--r--src/mem/cache/tags/base.cc2
-rw-r--r--src/mem/cache/tags/base.hh5
-rw-r--r--src/mem/cache/tags/base_set_assoc.cc3
-rw-r--r--src/mem/cache/tags/base_set_assoc.hh12
-rw-r--r--src/mem/cache/tags/fa_lru.cc4
-rw-r--r--src/mem/cache/tags/fa_lru.hh9
6 files changed, 6 insertions, 29 deletions
diff --git a/src/mem/cache/tags/base.cc b/src/mem/cache/tags/base.cc
index 47a43fb7e..8d2322e51 100644
--- a/src/mem/cache/tags/base.cc
+++ b/src/mem/cache/tags/base.cc
@@ -55,7 +55,7 @@ using namespace std;
BaseTags::BaseTags(const Params *p)
: ClockedObject(p), blkSize(p->block_size), size(p->size),
- hitLatency(p->hit_latency), cache(nullptr), warmupBound(0),
+ accessLatency(p->hit_latency), cache(nullptr), warmupBound(0),
warmedUp(false), numBlocks(0)
{
}
diff --git a/src/mem/cache/tags/base.hh b/src/mem/cache/tags/base.hh
index 9e1fb1972..03b6cfed8 100644
--- a/src/mem/cache/tags/base.hh
+++ b/src/mem/cache/tags/base.hh
@@ -68,9 +68,8 @@ class BaseTags : public ClockedObject
const unsigned blkSize;
/** The size of the cache. */
const unsigned size;
- /** The hit latency of the cache. */
- const Cycles hitLatency;
-
+ /** The access latency of the cache. */
+ const Cycles accessLatency;
/** Pointer to the parent cache. */
BaseCache *cache;
diff --git a/src/mem/cache/tags/base_set_assoc.cc b/src/mem/cache/tags/base_set_assoc.cc
index bb0c20141..3c8371edb 100644
--- a/src/mem/cache/tags/base_set_assoc.cc
+++ b/src/mem/cache/tags/base_set_assoc.cc
@@ -68,9 +68,6 @@ BaseSetAssoc::BaseSetAssoc(const Params *p)
if (assoc <= 0) {
fatal("associativity must be greater than zero");
}
- if (hitLatency <= 0) {
- fatal("access latency must be greater than zero");
- }
blkMask = blkSize - 1;
setShift = floorLog2(blkSize);
diff --git a/src/mem/cache/tags/base_set_assoc.hh b/src/mem/cache/tags/base_set_assoc.hh
index ac575d2ff..0107aafaf 100644
--- a/src/mem/cache/tags/base_set_assoc.hh
+++ b/src/mem/cache/tags/base_set_assoc.hh
@@ -178,7 +178,7 @@ public:
Addr tag = extractTag(addr);
int set = extractSet(addr);
BlkType *blk = sets[set].findBlk(tag, is_secure);
- lat = hitLatency;
+ lat = accessLatency;;
// Access all tags in parallel, hence one in each way. The data side
// either accesses all blocks in parallel, or one block sequentially on
@@ -195,7 +195,7 @@ public:
if (blk != NULL) {
if (blk->whenReady > curTick()
&& cache->ticksToCycles(blk->whenReady - curTick())
- > hitLatency) {
+ > accessLatency) {
lat = cache->ticksToCycles(blk->whenReady - curTick());
}
blk->refCount += 1;
@@ -343,14 +343,6 @@ public:
}
/**
- * Return the hit latency.
- * @return the hit latency.
- */
- Cycles getHitLatency() const
- {
- return hitLatency;
- }
- /**
*iterated through all blocks and clear all locks
*Needed to clear all lock tracking at once
*/
diff --git a/src/mem/cache/tags/fa_lru.cc b/src/mem/cache/tags/fa_lru.cc
index 6a63da673..ffe2cbf25 100644
--- a/src/mem/cache/tags/fa_lru.cc
+++ b/src/mem/cache/tags/fa_lru.cc
@@ -60,8 +60,6 @@ FALRU::FALRU(const Params *p)
if (!isPowerOf2(blkSize))
fatal("cache block size (in bytes) `%d' must be a power of two",
blkSize);
- if (!(hitLatency > 0))
- fatal("Access latency in cycles must be at least one cycle");
if (!isPowerOf2(size))
fatal("Cache Size must be power of 2 for now");
@@ -202,7 +200,7 @@ FALRU::accessBlock(Addr addr, bool is_secure, Cycles &lat, int context_src,
*inCache = tmp_in_cache;
}
- lat = hitLatency;
+ lat = accessLatency;
//assert(check());
return blk;
}
diff --git a/src/mem/cache/tags/fa_lru.hh b/src/mem/cache/tags/fa_lru.hh
index ef13b2c79..07a31c154 100644
--- a/src/mem/cache/tags/fa_lru.hh
+++ b/src/mem/cache/tags/fa_lru.hh
@@ -210,15 +210,6 @@ public:
void insertBlock(PacketPtr pkt, BlkType *blk);
/**
- * Return the hit latency of this cache.
- * @return The hit latency.
- */
- Cycles getHitLatency() const
- {
- return hitLatency;
- }
-
- /**
* Return the block size of this cache.
* @return The block size.
*/