diff options
Diffstat (limited to 'src/mem/cache')
| -rw-r--r-- | src/mem/cache/base.cc | 13 | ||||
| -rw-r--r-- | src/mem/cache/base.hh | 10 |
2 files changed, 6 insertions, 17 deletions
diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc index 7863edde0..09e3d0869 100644 --- a/src/mem/cache/base.cc +++ b/src/mem/cache/base.cc @@ -38,6 +38,7 @@ #include "debug/Cache.hh" #include "mem/cache/base.hh" #include "mem/cache/mshr.hh" +#include "sim/full_system.hh" using namespace std; @@ -151,11 +152,7 @@ BaseCache::regStats() const string &cstr = cmd.toString(); hits[access_idx] -#if FULL_SYSTEM - .init(_numCpus + 1) -#else - .init(_numCpus) -#endif + .init(FullSystem ? (_numCpus + 1) : _numCpus) .name(name() + "." + cstr + "_hits") .desc("number of " + cstr + " hits") .flags(total | nozero | nonan) @@ -192,11 +189,7 @@ BaseCache::regStats() const string &cstr = cmd.toString(); misses[access_idx] -#if FULL_SYSTEM - .init(_numCpus + 1) -#else - .init(_numCpus) -#endif + .init(FullSystem ? (_numCpus + 1) : _numCpus) .name(name() + "." + cstr + "_misses") .desc("number of " + cstr + " misses") .flags(total | nozero | nonan) diff --git a/src/mem/cache/base.hh b/src/mem/cache/base.hh index 297692b32..8c39a2400 100644 --- a/src/mem/cache/base.hh +++ b/src/mem/cache/base.hh @@ -47,7 +47,6 @@ #include "base/statistics.hh" #include "base/trace.hh" #include "base/types.hh" -#include "config/full_system.hh" #include "debug/Cache.hh" #include "debug/CachePort.hh" #include "mem/cache/mshr_queue.hh" @@ -57,6 +56,7 @@ #include "mem/tport.hh" #include "params/BaseCache.hh" #include "sim/eventq.hh" +#include "sim/full_system.hh" #include "sim/sim_exit.hh" class MSHR; @@ -505,12 +505,10 @@ class BaseCache : public MemObject * available, meanwhile writeback hit/miss stats are not used * in any aggregate hit/miss calculations, so just lump them all * in bucket 0 */ -#if FULL_SYSTEM - } else if (id == -1) { + } else if (FullSystem && id == -1) { // Device accesses have id -1 // lump device accesses into their own bucket misses[pkt->cmdToIndex()][_numCpus]++; -#endif } else { misses[pkt->cmdToIndex()][id % _numCpus]++; } @@ -533,12 +531,10 @@ class BaseCache : public MemObject if (pkt->cmd == MemCmd::Writeback) { assert(id == -1); hits[pkt->cmdToIndex()][0]++; -#if FULL_SYSTEM - } else if (id == -1) { + } else if (FullSystem && id == -1) { // Device accesses have id -1 // lump device accesses into their own bucket hits[pkt->cmdToIndex()][_numCpus]++; -#endif } else { /* the % is necessary in case there are switch cpus */ hits[pkt->cmdToIndex()][id % _numCpus]++; |