diff options
Diffstat (limited to 'src/mem/cache')
36 files changed, 545 insertions, 587 deletions
diff --git a/src/mem/cache/base_cache.cc b/src/mem/cache/base_cache.cc index 51b4ed55e..0694aae6e 100644 --- a/src/mem/cache/base_cache.cc +++ b/src/mem/cache/base_cache.cc @@ -33,11 +33,10 @@ * Definition of BaseCache functions. */ +#include "cpu/base.hh" +#include "cpu/smt.hh" #include "mem/cache/base_cache.hh" #include "mem/cache/miss/mshr.hh" -#include "mem/packet_impl.hh" -#include "cpu/smt.hh" -#include "cpu/base.hh" using namespace std; @@ -72,7 +71,7 @@ BaseCache::CachePort::deviceBlockSize() } bool -BaseCache::CachePort::recvTiming(Packet *pkt) +BaseCache::CachePort::recvTiming(PacketPtr pkt) { if (isCpuSide && !pkt->req->isUncacheable() @@ -100,48 +99,23 @@ BaseCache::CachePort::recvTiming(Packet *pkt) } Tick -BaseCache::CachePort::recvAtomic(Packet *pkt) +BaseCache::CachePort::recvAtomic(PacketPtr pkt) { return cache->doAtomicAccess(pkt, isCpuSide); } void -BaseCache::CachePort::recvFunctional(Packet *pkt) +BaseCache::CachePort::recvFunctional(PacketPtr pkt) { //Check storage here first - list<Packet *>::iterator i = drainList.begin(); - list<Packet *>::iterator end = drainList.end(); + list<PacketPtr>::iterator i = drainList.begin(); + list<PacketPtr>::iterator end = drainList.end(); for (; i != end; ++i) { - Packet * target = *i; + PacketPtr target = *i; // If the target contains data, and it overlaps the // probed request, need to update data if (target->intersect(pkt)) { - uint8_t* pkt_data; - uint8_t* write_data; - int data_size; - if (target->getAddr() < pkt->getAddr()) { - int offset = pkt->getAddr() - target->getAddr(); - pkt_data = pkt->getPtr<uint8_t>(); - write_data = target->getPtr<uint8_t>() + offset; - data_size = target->getSize() - offset; - assert(data_size > 0); - if (data_size > pkt->getSize()) - data_size = pkt->getSize(); - } else { - int offset = target->getAddr() - pkt->getAddr(); - pkt_data = pkt->getPtr<uint8_t>() + offset; - write_data = target->getPtr<uint8_t>(); - data_size = pkt->getSize() - offset; - assert(data_size > pkt->getSize()); - if (data_size > target->getSize()) - data_size = target->getSize(); - } - - if (pkt->isWrite()) { - memcpy(pkt_data, write_data, data_size); - } else { - memcpy(write_data, pkt_data, data_size); - } + fixPacket(pkt, target); } } cache->doFunctionalAccess(pkt, isCpuSide); @@ -150,7 +124,7 @@ BaseCache::CachePort::recvFunctional(Packet *pkt) void BaseCache::CachePort::recvRetry() { - Packet *pkt; + PacketPtr pkt; assert(waitingOnRetry); if (!drainList.empty()) { DPRINTF(CachePort, "%s attempting to send a retry for response\n", name()); @@ -182,7 +156,7 @@ BaseCache::CachePort::recvRetry() pkt = cache->getPacket(); MSHR* mshr = (MSHR*) pkt->senderState; //Copy the packet, it may be modified/destroyed elsewhere - Packet * copyPkt = new Packet(*pkt); + PacketPtr copyPkt = new Packet(*pkt); copyPkt->dataStatic<uint8_t>(pkt->getPtr<uint8_t>()); mshr->pkt = copyPkt; @@ -258,7 +232,7 @@ BaseCache::CacheEvent::CacheEvent(CachePort *_cachePort) pkt = NULL; } -BaseCache::CacheEvent::CacheEvent(CachePort *_cachePort, Packet *_pkt) +BaseCache::CacheEvent::CacheEvent(CachePort *_cachePort, PacketPtr _pkt) : Event(&mainEventQueue, CPU_Tick_Pri), cachePort(_cachePort), pkt(_pkt) { this->setFlags(AutoDelete); @@ -302,7 +276,7 @@ BaseCache::CacheEvent::process() pkt = cachePort->cache->getPacket(); MSHR* mshr = (MSHR*) pkt->senderState; //Copy the packet, it may be modified/destroyed elsewhere - Packet * copyPkt = new Packet(*pkt); + PacketPtr copyPkt = new Packet(*pkt); copyPkt->dataStatic<uint8_t>(pkt->getPtr<uint8_t>()); mshr->pkt = copyPkt; @@ -332,7 +306,7 @@ BaseCache::CacheEvent::process() pkt = cachePort->cache->getCoherencePacket(); MSHR* cshr = (MSHR*) pkt->senderState; bool success = cachePort->sendTiming(pkt); - cachePort->cache->sendResult(pkt, cshr, success); + cachePort->cache->sendCoherenceResult(pkt, cshr, success); cachePort->waitingOnRetry = !success; if (cachePort->waitingOnRetry) DPRINTF(CachePort, "%s now waiting on a retry\n", cachePort->name()); diff --git a/src/mem/cache/base_cache.hh b/src/mem/cache/base_cache.hh index 93830b04f..565280aef 100644 --- a/src/mem/cache/base_cache.hh +++ b/src/mem/cache/base_cache.hh @@ -85,11 +85,11 @@ class BaseCache : public MemObject CachePort(const std::string &_name, BaseCache *_cache, bool _isCpuSide); protected: - virtual bool recvTiming(Packet *pkt); + virtual bool recvTiming(PacketPtr pkt); - virtual Tick recvAtomic(Packet *pkt); + virtual Tick recvAtomic(PacketPtr pkt); - virtual void recvFunctional(Packet *pkt); + virtual void recvFunctional(PacketPtr pkt); virtual void recvStatusChange(Status status); @@ -113,23 +113,25 @@ class BaseCache : public MemObject bool waitingOnRetry; - std::list<Packet *> drainList; + std::list<PacketPtr> drainList; }; struct CacheEvent : public Event { CachePort *cachePort; - Packet *pkt; + PacketPtr pkt; CacheEvent(CachePort *_cachePort); - CacheEvent(CachePort *_cachePort, Packet *_pkt); + CacheEvent(CachePort *_cachePort, PacketPtr _pkt); void process(); const char *description(); }; - protected: + public: //Made public so coherence can get at it. CachePort *cpuSidePort; + + protected: CachePort *memSidePort; bool snoopRangesSent; @@ -139,17 +141,17 @@ class BaseCache : public MemObject private: //To be defined in cache_impl.hh not in base class - virtual bool doTimingAccess(Packet *pkt, CachePort *cachePort, bool isCpuSide) + virtual bool doTimingAccess(PacketPtr pkt, CachePort *cachePort, bool isCpuSide) { fatal("No implementation"); } - virtual Tick doAtomicAccess(Packet *pkt, bool isCpuSide) + virtual Tick doAtomicAccess(PacketPtr pkt, bool isCpuSide) { fatal("No implementation"); } - virtual void doFunctionalAccess(Packet *pkt, bool isCpuSide) + virtual void doFunctionalAccess(PacketPtr pkt, bool isCpuSide) { fatal("No implementation"); } @@ -170,23 +172,23 @@ class BaseCache : public MemObject } } - virtual Packet *getPacket() + virtual PacketPtr getPacket() { fatal("No implementation"); } - virtual Packet *getCoherencePacket() + virtual PacketPtr getCoherencePacket() { fatal("No implementation"); } - virtual void sendResult(Packet* &pkt, MSHR* mshr, bool success) + virtual void sendResult(PacketPtr &pkt, MSHR* mshr, bool success) { fatal("No implementation"); } - virtual void sendCoherenceResult(Packet* &pkt, MSHR* mshr, bool success) + virtual void sendCoherenceResult(PacketPtr &pkt, MSHR* mshr, bool success) { fatal("No implementation"); @@ -517,7 +519,7 @@ class BaseCache : public MemObject * @param pkt The request being responded to. * @param time The time the response is ready. */ - void respond(Packet *pkt, Tick time) + void respond(PacketPtr pkt, Tick time) { if (pkt->needsResponse()) { CacheEvent *reqCpu = new CacheEvent(cpuSidePort, pkt); @@ -537,7 +539,7 @@ class BaseCache : public MemObject * @param pkt The request to respond to. * @param time The time the response is ready. */ - void respondToMiss(Packet *pkt, Tick time) + void respondToMiss(PacketPtr pkt, Tick time) { if (!pkt->req->isUncacheable()) { missLatency[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/] += time - pkt->time; @@ -559,7 +561,7 @@ class BaseCache : public MemObject * Suppliess the data if cache to cache transfers are enabled. * @param pkt The bus transaction to fulfill. */ - void respondToSnoop(Packet *pkt, Tick time) + void respondToSnoop(PacketPtr pkt, Tick time) { assert (pkt->needsResponse()); CacheEvent *reqMem = new CacheEvent(memSidePort, pkt); diff --git a/src/mem/cache/cache.hh b/src/mem/cache/cache.hh index 07d9d6336..1f3b087bb 100644 --- a/src/mem/cache/cache.hh +++ b/src/mem/cache/cache.hh @@ -96,7 +96,7 @@ class Cache : public BaseCache * A permanent mem req to always be used to cause invalidations. * Used to append to target list, to cause an invalidation. */ - Packet * invalidatePkt; + PacketPtr invalidatePkt; Request *invalidateReq; public: @@ -127,12 +127,12 @@ class Cache : public BaseCache /** Instantiates a basic cache object. */ Cache(const std::string &_name, Params ¶ms); - virtual bool doTimingAccess(Packet *pkt, CachePort *cachePort, + virtual bool doTimingAccess(PacketPtr pkt, CachePort *cachePort, bool isCpuSide); - virtual Tick doAtomicAccess(Packet *pkt, bool isCpuSide); + virtual Tick doAtomicAccess(PacketPtr pkt, bool isCpuSide); - virtual void doFunctionalAccess(Packet *pkt, bool isCpuSide); + virtual void doFunctionalAccess(PacketPtr pkt, bool isCpuSide); virtual void recvStatusChange(Port::Status status, bool isCpuSide); @@ -143,47 +143,47 @@ class Cache : public BaseCache * @param pkt The request to perform. * @return The result of the access. */ - bool access(Packet * &pkt); + bool access(PacketPtr &pkt); /** * Selects a request to send on the bus. * @return The memory request to service. */ - virtual Packet * getPacket(); + virtual PacketPtr getPacket(); /** * Was the request was sent successfully? * @param pkt The request. * @param success True if the request was sent successfully. */ - virtual void sendResult(Packet * &pkt, MSHR* mshr, bool success); + virtual void sendResult(PacketPtr &pkt, MSHR* mshr, bool success); /** * Was the CSHR request was sent successfully? * @param pkt The request. * @param success True if the request was sent successfully. */ - virtual void sendCoherenceResult(Packet * &pkt, MSHR* cshr, bool success); + virtual void sendCoherenceResult(PacketPtr &pkt, MSHR* cshr, bool success); /** * Handles a response (cache line fill/write ack) from the bus. * @param pkt The request being responded to. */ - void handleResponse(Packet * &pkt); + void handleResponse(PacketPtr &pkt); /** * Selects a coherence message to forward to lower levels of the hierarchy. * @return The coherence message to forward. */ - virtual Packet * getCoherencePacket(); + virtual PacketPtr getCoherencePacket(); /** * Snoops bus transactions to maintain coherence. * @param pkt The current bus transaction. */ - void snoop(Packet * &pkt); + void snoop(PacketPtr &pkt); - void snoopResponse(Packet * &pkt); + void snoopResponse(PacketPtr &pkt); /** * Invalidates the block containing address if found. @@ -224,7 +224,7 @@ class Cache : public BaseCache * request. * @return The estimated completion time. */ - Tick probe(Packet * &pkt, bool update, CachePort * otherSidePort); + Tick probe(PacketPtr &pkt, bool update, CachePort * otherSidePort); /** * Snoop for the provided request in the cache and return the estimated @@ -235,7 +235,7 @@ class Cache : public BaseCache * request. * @return The estimated completion time. */ - Tick snoopProbe(Packet * &pkt); + Tick snoopProbe(PacketPtr &pkt); }; #endif // __CACHE_HH__ diff --git a/src/mem/cache/cache_blk.hh b/src/mem/cache/cache_blk.hh index 078c82d82..7b999e4b1 100644 --- a/src/mem/cache/cache_blk.hh +++ b/src/mem/cache/cache_blk.hh @@ -35,8 +35,11 @@ #ifndef __CACHE_BLK_HH__ #define __CACHE_BLK_HH__ +#include <list> + #include "sim/root.hh" // for Tick #include "arch/isa_traits.hh" // for Addr +#include "mem/request.hh" /** * Cache block status bit assignments @@ -96,6 +99,35 @@ class CacheBlk /** Number of references to this block since it was brought in. */ int refCount; + protected: + /** + * Represents that the indicated thread context has a "lock" on + * the block, in the LL/SC sense. + */ + class Lock { + public: + int cpuNum; // locking CPU + int threadNum; // locking thread ID within CPU + + // check for matching execution context + bool matchesContext(Request *req) + { + return (cpuNum == req->getCpuNum() && + threadNum == req->getThreadNum()); + } + + Lock(Request *req) + : cpuNum(req->getCpuNum()), threadNum(req->getThreadNum()) + { + } + }; + + /** List of thread contexts that have performed a load-locked (LL) + * on the block since the last store. */ + std::list<Lock> lockList; + + public: + CacheBlk() : asid(-1), tag(0), data(0) ,size(0), status(0), whenReady(0), set(-1), refCount(0) @@ -175,7 +207,58 @@ class CacheBlk return (status & BlkHWPrefetched) != 0; } + /** + * Track the fact that a local locked was issued to the block. If + * multiple LLs get issued from the same context we could have + * redundant records on the list, but that's OK, as they'll all + * get blown away at the next store. + */ + void trackLoadLocked(Request *req) + { + assert(req->isLocked()); + lockList.push_front(Lock(req)); + } + + /** + * Clear the list of valid load locks. Should be called whenever + * block is written to or invalidated. + */ + void clearLoadLocks() { lockList.clear(); } + /** + * Handle interaction of load-locked operations and stores. + * @return True if write should proceed, false otherwise. Returns + * false only in the case of a failed store conditional. + */ + bool checkWrite(Request *req) + { + if (req->isLocked()) { + // it's a store conditional... have to check for matching + // load locked. + bool success = false; + + for (std::list<Lock>::iterator i = lockList.begin(); + i != lockList.end(); ++i) + { + if (i->matchesContext(req)) { + // it's a store conditional, and as far as the memory + // system can tell, the requesting context's lock is + // still valid. + success = true; + break; + } + } + + req->setScResult(success ? 1 : 0); + clearLoadLocks(); + return success; + } else { + // for *all* stores (conditional or otherwise) we have to + // clear the list of load-locks as they're all invalid now. + clearLoadLocks(); + return true; + } + } }; #endif //__CACHE_BLK_HH__ diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh index 520e5abb5..3c47762f6 100644 --- a/src/mem/cache/cache_impl.hh +++ b/src/mem/cache/cache_impl.hh @@ -56,7 +56,7 @@ template<class TagStore, class Buffering, class Coherence> bool Cache<TagStore,Buffering,Coherence>:: -doTimingAccess(Packet *pkt, CachePort *cachePort, bool isCpuSide) +doTimingAccess(PacketPtr pkt, CachePort *cachePort, bool isCpuSide) { if (isCpuSide) { @@ -82,15 +82,10 @@ doTimingAccess(Packet *pkt, CachePort *cachePort, bool isCpuSide) template<class TagStore, class Buffering, class Coherence> Tick Cache<TagStore,Buffering,Coherence>:: -doAtomicAccess(Packet *pkt, bool isCpuSide) +doAtomicAccess(PacketPtr pkt, bool isCpuSide) { if (isCpuSide) { - //Temporary solution to LL/SC - if (pkt->isWrite() && (pkt->req->isLocked())) { - pkt->req->setScResult(1); - } - probe(pkt, true, NULL); //TEMP ALWAYS SUCCES FOR NOW pkt->result = Packet::Success; @@ -109,18 +104,13 @@ doAtomicAccess(Packet *pkt, bool isCpuSide) template<class TagStore, class Buffering, class Coherence> void Cache<TagStore,Buffering,Coherence>:: -doFunctionalAccess(Packet *pkt, bool isCpuSide) +doFunctionalAccess(PacketPtr pkt, bool isCpuSide) { if (isCpuSide) { //TEMP USE CPU?THREAD 0 0 pkt->req->setThreadContext(0,0); - //Temporary solution to LL/SC - if (pkt->isWrite() && (pkt->req->isLocked())) { - assert("Can't handle LL/SC on functional path\n"); - } - probe(pkt, false, memSidePort); //TEMP ALWAYS SUCCESFUL FOR NOW pkt->result = Packet::Success; @@ -241,18 +231,26 @@ Cache<TagStore,Buffering,Coherence>::access(PacketPtr &pkt) exitSimLoop("A cache reached the maximum miss count"); } } - missQueue->handleMiss(pkt, size, curTick + hitLatency); -// return MA_CACHE_MISS; + + if (pkt->flags & SATISFIED) { + // happens when a store conditional fails because it missed + // the cache completely + if (pkt->needsResponse()) + respond(pkt, curTick+lat); + } else { + missQueue->handleMiss(pkt, size, curTick + hitLatency); + } + return true; } template<class TagStore, class Buffering, class Coherence> -Packet * +PacketPtr Cache<TagStore,Buffering,Coherence>::getPacket() { assert(missQueue->havePending()); - Packet * pkt = missQueue->getPacket(); + PacketPtr pkt = missQueue->getPacket(); if (pkt) { if (!pkt->req->isUncacheable()) { if (pkt->cmd == Packet::HardPFReq) @@ -316,7 +314,7 @@ Cache<TagStore,Buffering,Coherence>::sendResult(PacketPtr &pkt, MSHR* mshr, template<class TagStore, class Buffering, class Coherence> void -Cache<TagStore,Buffering,Coherence>::handleResponse(Packet * &pkt) +Cache<TagStore,Buffering,Coherence>::handleResponse(PacketPtr &pkt) { BlkType *blk = NULL; if (pkt->senderState) { @@ -358,7 +356,7 @@ Cache<TagStore,Buffering,Coherence>::handleResponse(Packet * &pkt) } template<class TagStore, class Buffering, class Coherence> -Packet * +PacketPtr Cache<TagStore,Buffering,Coherence>::getCoherencePacket() { return coherence->getPacket(); @@ -366,7 +364,7 @@ Cache<TagStore,Buffering,Coherence>::getCoherencePacket() template<class TagStore, class Buffering, class Coherence> void -Cache<TagStore,Buffering,Coherence>::sendCoherenceResult(Packet* &pkt, +Cache<TagStore,Buffering,Coherence>::sendCoherenceResult(PacketPtr &pkt, MSHR *cshr, bool success) { @@ -376,17 +374,22 @@ Cache<TagStore,Buffering,Coherence>::sendCoherenceResult(Packet* &pkt, template<class TagStore, class Buffering, class Coherence> void -Cache<TagStore,Buffering,Coherence>::snoop(Packet * &pkt) +Cache<TagStore,Buffering,Coherence>::snoop(PacketPtr &pkt) { if (pkt->req->isUncacheable()) { //Can't get a hit on an uncacheable address //Revisit this for multi level coherence return; } + + //Send a timing (true) invalidate up if the protocol calls for it + coherence->propogateInvalidate(pkt, true); + Addr blk_addr = pkt->getAddr() & ~(Addr(blkSize-1)); BlkType *blk = tags->findBlock(pkt); MSHR *mshr = missQueue->findMSHR(blk_addr); - if (coherence->hasProtocol()) { //@todo Move this into handle bus req + if (coherence->hasProtocol() || pkt->isInvalidate()) { + //@todo Move this into handle bus req //If we find an mshr, and it is in service, we need to NACK or //invalidate if (mshr) { @@ -490,7 +493,7 @@ Cache<TagStore,Buffering,Coherence>::snoop(Packet * &pkt) template<class TagStore, class Buffering, class Coherence> void -Cache<TagStore,Buffering,Coherence>::snoopResponse(Packet * &pkt) +Cache<TagStore,Buffering,Coherence>::snoopResponse(PacketPtr &pkt) { //Need to handle the response, if NACKED if (pkt->flags & NACKED_LINE) { @@ -520,7 +523,7 @@ Cache<TagStore,Buffering,Coherence>::invalidateBlk(Addr addr) */ template<class TagStore, class Buffering, class Coherence> Tick -Cache<TagStore,Buffering,Coherence>::probe(Packet * &pkt, bool update, +Cache<TagStore,Buffering,Coherence>::probe(PacketPtr &pkt, bool update, CachePort* otherSidePort) { // MemDebug::cacheProbe(pkt); @@ -536,6 +539,13 @@ Cache<TagStore,Buffering,Coherence>::probe(Packet * &pkt, bool update, } } + if (!update && (pkt->isWrite() || (otherSidePort == cpuSidePort))) { + // Still need to change data in all locations. + otherSidePort->sendFunctional(pkt); + if (pkt->isRead() && pkt->result == Packet::Success) + return 0; + } + PacketList writebacks; int lat; BlkType *blk = tags->handleAccess(pkt, lat, writebacks, update); @@ -544,179 +554,127 @@ Cache<TagStore,Buffering,Coherence>::probe(Packet * &pkt, bool update, pkt->getAddr() & (((ULL(1))<<48)-1), (blk) ? "hit" : "miss", pkt->getAddr() & ~((Addr)blkSize - 1)); - if (!blk) { - // Need to check for outstanding misses and writes - Addr blk_addr = pkt->getAddr() & ~(blkSize - 1); - - // There can only be one matching outstanding miss. - MSHR* mshr = missQueue->findMSHR(blk_addr); - - // There can be many matching outstanding writes. - std::vector<MSHR*> writes; - missQueue->findWrites(blk_addr, writes); - - if (!update) { - otherSidePort->sendFunctional(pkt); - - // Check for data in MSHR and writebuffer. - if (mshr) { - warn("Found outstanding miss on an non-update probe"); - MSHR::TargetList *targets = mshr->getTargetList(); - MSHR::TargetList::iterator i = targets->begin(); - MSHR::TargetList::iterator end = targets->end(); - for (; i != end; ++i) { - Packet * target = *i; - // If the target contains data, and it overlaps the - // probed request, need to update data - if (target->isWrite() && target->intersect(pkt)) { - uint8_t* pkt_data; - uint8_t* write_data; - int data_size; - if (target->getAddr() < pkt->getAddr()) { - int offset = pkt->getAddr() - target->getAddr(); - pkt_data = pkt->getPtr<uint8_t>(); - write_data = target->getPtr<uint8_t>() + offset; - data_size = target->getSize() - offset; - assert(data_size > 0); - if (data_size > pkt->getSize()) - data_size = pkt->getSize(); - } else { - int offset = target->getAddr() - pkt->getAddr(); - pkt_data = pkt->getPtr<uint8_t>() + offset; - write_data = target->getPtr<uint8_t>(); - data_size = pkt->getSize() - offset; - assert(data_size > pkt->getSize()); - if (data_size > target->getSize()) - data_size = target->getSize(); - } - - if (pkt->isWrite()) { - memcpy(pkt_data, write_data, data_size); - } else { - memcpy(write_data, pkt_data, data_size); - } - } - } - } - for (int i = 0; i < writes.size(); ++i) { - Packet * write = writes[i]->pkt; - if (write->intersect(pkt)) { - warn("Found outstanding write on an non-update probe"); - uint8_t* pkt_data; - uint8_t* write_data; - int data_size; - if (write->getAddr() < pkt->getAddr()) { - int offset = pkt->getAddr() - write->getAddr(); - pkt_data = pkt->getPtr<uint8_t>(); - write_data = write->getPtr<uint8_t>() + offset; - data_size = write->getSize() - offset; - assert(data_size > 0); - if (data_size > pkt->getSize()) - data_size = pkt->getSize(); - } else { - int offset = write->getAddr() - pkt->getAddr(); - pkt_data = pkt->getPtr<uint8_t>() + offset; - write_data = write->getPtr<uint8_t>(); - data_size = pkt->getSize() - offset; - assert(data_size > pkt->getSize()); - if (data_size > write->getSize()) - data_size = write->getSize(); - } - if (pkt->isWrite()) { - memcpy(pkt_data, write_data, data_size); - } else { - memcpy(write_data, pkt_data, data_size); - } + // Need to check for outstanding misses and writes + Addr blk_addr = pkt->getAddr() & ~(blkSize - 1); + // There can only be one matching outstanding miss. + MSHR* mshr = missQueue->findMSHR(blk_addr); + + // There can be many matching outstanding writes. + std::vector<MSHR*> writes; + missQueue->findWrites(blk_addr, writes); + + if (!update) { + // Check for data in MSHR and writebuffer. + if (mshr) { + MSHR::TargetList *targets = mshr->getTargetList(); + MSHR::TargetList::iterator i = targets->begin(); + MSHR::TargetList::iterator end = targets->end(); + for (; i != end; ++i) { + PacketPtr target = *i; + // If the target contains data, and it overlaps the + // probed request, need to update data + if (target->intersect(pkt)) { + fixPacket(pkt, target); } } - return 0; - } else { - // update the cache state and statistics - if (mshr || !writes.empty()){ - // Can't handle it, return pktuest unsatisfied. - panic("Atomic access ran into outstanding MSHR's or WB's!"); + } + for (int i = 0; i < writes.size(); ++i) { + PacketPtr write = writes[i]->pkt; + if (write->intersect(pkt)) { + fixPacket(pkt, write); } - if (!pkt->req->isUncacheable()) { + } + if (pkt->isRead() + && pkt->result != Packet::Success + && otherSidePort == memSidePort) { + otherSidePort->sendFunctional(pkt); + assert(pkt->result == Packet::Success); + } + return 0; + } else if (!blk && !(pkt->flags & SATISFIED)) { + // update the cache state and statistics + if (mshr || !writes.empty()){ + // Can't handle it, return pktuest unsatisfied. + panic("Atomic access ran into outstanding MSHR's or WB's!"); + } + if (!pkt->req->isUncacheable()) { // Fetch the cache block to fill - BlkType *blk = tags->findBlock(pkt); - Packet::Command temp_cmd = coherence->getBusCmd(pkt->cmd, - (blk)? blk->status : 0); + BlkType *blk = tags->findBlock(pkt); + Packet::Command temp_cmd = coherence->getBusCmd(pkt->cmd, + (blk)? blk->status : 0); - Packet * busPkt = new Packet(pkt->req,temp_cmd, -1, blkSize); + PacketPtr busPkt = new Packet(pkt->req,temp_cmd, -1, blkSize); - busPkt->allocate(); + busPkt->allocate(); - busPkt->time = curTick; + busPkt->time = curTick; - DPRINTF(Cache, "Sending a atomic %s for %x blk_addr: %x\n", - busPkt->cmdString(), - busPkt->getAddr() & (((ULL(1))<<48)-1), - busPkt->getAddr() & ~((Addr)blkSize - 1)); + DPRINTF(Cache, "Sending a atomic %s for %x blk_addr: %x\n", + busPkt->cmdString(), + busPkt->getAddr() & (((ULL(1))<<48)-1), + busPkt->getAddr() & ~((Addr)blkSize - 1)); - lat = memSidePort->sendAtomic(busPkt); + lat = memSidePort->sendAtomic(busPkt); - //Be sure to flip the response to a request for coherence - if (busPkt->needsResponse()) { - busPkt->makeAtomicResponse(); - } + //Be sure to flip the response to a request for coherence + if (busPkt->needsResponse()) { + busPkt->makeAtomicResponse(); + } /* if (!(busPkt->flags & SATISFIED)) { - // blocked at a higher level, just return - return 0; - } +// blocked at a higher level, just return +return 0; +} */ misses[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++; - CacheBlk::State old_state = (blk) ? blk->status : 0; - CacheBlk::State new_state = - coherence->getNewState(busPkt, old_state); - DPRINTF(Cache, + CacheBlk::State old_state = (blk) ? blk->status : 0; + CacheBlk::State new_state = + coherence->getNewState(busPkt, old_state); + DPRINTF(Cache, "Receive response:%s for blk addr %x in state %i\n", - busPkt->cmdString(), - busPkt->getAddr() & (((ULL(1))<<48)-1), old_state); - if (old_state != new_state) + busPkt->cmdString(), + busPkt->getAddr() & (((ULL(1))<<48)-1), old_state); + if (old_state != new_state) DPRINTF(Cache, "Block for blk addr %x moving from " "state %i to %i\n", busPkt->getAddr() & (((ULL(1))<<48)-1), old_state, new_state); - tags->handleFill(blk, busPkt, - new_state, - writebacks, pkt); - //Free the packet - delete busPkt; - - // Handle writebacks if needed - while (!writebacks.empty()){ - Packet *wbPkt = writebacks.front(); - memSidePort->sendAtomic(wbPkt); - writebacks.pop_front(); - delete wbPkt; - } - return lat + hitLatency; - } else { - return memSidePort->sendAtomic(pkt); + tags->handleFill(blk, busPkt, + new_state, + writebacks, pkt); + //Free the packet + delete busPkt; + + // Handle writebacks if needed + while (!writebacks.empty()){ + PacketPtr wbPkt = writebacks.front(); + memSidePort->sendAtomic(wbPkt); + writebacks.pop_front(); + delete wbPkt; } + return lat + hitLatency; + } else { + return memSidePort->sendAtomic(pkt); } } else { - // There was a cache hit. - // Handle writebacks if needed - while (!writebacks.empty()){ - memSidePort->sendAtomic(writebacks.front()); - writebacks.pop_front(); - } + if (blk) { + // There was a cache hit. + // Handle writebacks if needed + while (!writebacks.empty()){ + memSidePort->sendAtomic(writebacks.front()); + writebacks.pop_front(); + } - if (update) { hits[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++; - } else if (pkt->isWrite()) { - // Still need to change data in all locations. - otherSidePort->sendFunctional(pkt); } + return hitLatency; } - fatal("Probe not handled.\n"); + return 0; } @@ -724,24 +682,27 @@ template<class TagStore, class Buffering, class Coherence> Tick Cache<TagStore,Buffering,Coherence>::snoopProbe(PacketPtr &pkt) { - Addr blk_addr = pkt->getAddr() & ~(Addr(blkSize-1)); - BlkType *blk = tags->findBlock(pkt); - MSHR *mshr = missQueue->findMSHR(blk_addr); - CacheBlk::State new_state = 0; - bool satisfy = coherence->handleBusRequest(pkt,blk,mshr, new_state); - if (satisfy) { - DPRINTF(Cache, "Cache snooped a %s request for addr %x and " - "now supplying data, new state is %i\n", - pkt->cmdString(), blk_addr, new_state); + //Send a atomic (false) invalidate up if the protocol calls for it + coherence->propogateInvalidate(pkt, false); + + Addr blk_addr = pkt->getAddr() & ~(Addr(blkSize-1)); + BlkType *blk = tags->findBlock(pkt); + MSHR *mshr = missQueue->findMSHR(blk_addr); + CacheBlk::State new_state = 0; + bool satisfy = coherence->handleBusRequest(pkt,blk,mshr, new_state); + if (satisfy) { + DPRINTF(Cache, "Cache snooped a %s request for addr %x and " + "now supplying data, new state is %i\n", + pkt->cmdString(), blk_addr, new_state); tags->handleSnoop(blk, new_state, pkt); return hitLatency; - } - if (blk) - DPRINTF(Cache, "Cache snooped a %s request for addr %x, " - "new state is %i\n", + } + if (blk) + DPRINTF(Cache, "Cache snooped a %s request for addr %x, " + "new state is %i\n", pkt->cmdString(), blk_addr, new_state); - tags->handleSnoop(blk, new_state); - return 0; + tags->handleSnoop(blk, new_state); + return 0; } diff --git a/src/mem/cache/coherence/coherence_protocol.cc b/src/mem/cache/coherence/coherence_protocol.cc index e28dda3dc..3d7721805 100644 --- a/src/mem/cache/coherence/coherence_protocol.cc +++ b/src/mem/cache/coherence/coherence_protocol.cc @@ -192,7 +192,7 @@ CoherenceProtocol::regStats() bool -CoherenceProtocol::invalidateTrans(BaseCache *cache, Packet * &pkt, +CoherenceProtocol::invalidateTrans(BaseCache *cache, PacketPtr &pkt, CacheBlk *blk, MSHR *mshr, CacheBlk::State & new_state) { @@ -203,18 +203,17 @@ CoherenceProtocol::invalidateTrans(BaseCache *cache, Packet * &pkt, bool -CoherenceProtocol::supplyTrans(BaseCache *cache, Packet * &pkt, +CoherenceProtocol::supplyTrans(BaseCache *cache, PacketPtr &pkt, CacheBlk *blk, MSHR *mshr, - CacheBlk::State & new_state - ) + CacheBlk::State & new_state) { return true; } bool -CoherenceProtocol::supplyAndGotoSharedTrans(BaseCache *cache, Packet * &pkt, +CoherenceProtocol::supplyAndGotoSharedTrans(BaseCache *cache, PacketPtr &pkt, CacheBlk *blk, MSHR *mshr, CacheBlk::State & new_state) @@ -226,7 +225,7 @@ CoherenceProtocol::supplyAndGotoSharedTrans(BaseCache *cache, Packet * &pkt, bool -CoherenceProtocol::supplyAndGotoOwnedTrans(BaseCache *cache, Packet * &pkt, +CoherenceProtocol::supplyAndGotoOwnedTrans(BaseCache *cache, PacketPtr &pkt, CacheBlk *blk, MSHR *mshr, CacheBlk::State & new_state) @@ -238,7 +237,7 @@ CoherenceProtocol::supplyAndGotoOwnedTrans(BaseCache *cache, Packet * &pkt, bool -CoherenceProtocol::supplyAndInvalidateTrans(BaseCache *cache, Packet * &pkt, +CoherenceProtocol::supplyAndInvalidateTrans(BaseCache *cache, PacketPtr &pkt, CacheBlk *blk, MSHR *mshr, CacheBlk::State & new_state) @@ -248,7 +247,7 @@ CoherenceProtocol::supplyAndInvalidateTrans(BaseCache *cache, Packet * &pkt, } bool -CoherenceProtocol::assertShared(BaseCache *cache, Packet * &pkt, +CoherenceProtocol::assertShared(BaseCache *cache, PacketPtr &pkt, CacheBlk *blk, MSHR *mshr, CacheBlk::State & new_state) @@ -263,182 +262,106 @@ CoherenceProtocol::CoherenceProtocol(const string &name, const bool doUpgrades) : SimObject(name) { - if ((protocol == "mosi" || protocol == "moesi") && !doUpgrades) { - cerr << "CoherenceProtocol: ownership protocols require upgrade transactions" - << "(write miss on owned block generates ReadExcl, which will clobber dirty block)" - << endl; - fatal(""); + // Python should catch this, but in case it doesn't... + if (!(protocol == "msi" || protocol == "mesi" || + protocol == "mosi" || protocol == "moesi")) { + fatal("CoherenceProtocol: unrecognized protocol %s\n", protocol); } - Packet::Command writeToSharedCmd = doUpgrades ? Packet::UpgradeReq : Packet::ReadExReq; - Packet::Command writeToSharedResp = doUpgrades ? Packet::UpgradeReq : Packet::ReadExResp; - -//@todo add in hardware prefetch to this list - if (protocol == "msi") { - // incoming requests: specify outgoing bus request - transitionTable[Invalid][Packet::ReadReq].onRequest(Packet::ReadReq); - transitionTable[Invalid][Packet::WriteReq].onRequest(Packet::ReadExReq); - transitionTable[Shared][Packet::WriteReq].onRequest(writeToSharedCmd); - //Prefetching causes a read - transitionTable[Invalid][Packet::SoftPFReq].onRequest(Packet::ReadReq); - transitionTable[Invalid][Packet::HardPFReq].onRequest(Packet::ReadReq); - - // on response to given request: specify new state - transitionTable[Invalid][Packet::ReadResp].onResponse(Shared); - transitionTable[Invalid][Packet::ReadExResp].onResponse(Modified); - transitionTable[Shared][writeToSharedResp].onResponse(Modified); - - // bus snoop transition functions - transitionTable[Invalid][Packet::ReadReq].onSnoop(nullTransition); - transitionTable[Invalid][Packet::ReadExReq].onSnoop(nullTransition); - transitionTable[Shared][Packet::ReadReq].onSnoop(nullTransition); - transitionTable[Shared][Packet::ReadExReq].onSnoop(invalidateTrans); - transitionTable[Modified][Packet::ReadExReq].onSnoop(supplyAndInvalidateTrans); - transitionTable[Modified][Packet::ReadReq].onSnoop(supplyAndGotoSharedTrans); - //Tansitions on seeing a DMA (writeInv(samelevel) or DMAInv) - transitionTable[Invalid][Packet::InvalidateReq].onSnoop(invalidateTrans); - transitionTable[Shared][Packet::InvalidateReq].onSnoop(invalidateTrans); - transitionTable[Modified][Packet::InvalidateReq].onSnoop(invalidateTrans); - transitionTable[Invalid][Packet::WriteInvalidateReq].onSnoop(invalidateTrans); - transitionTable[Shared][Packet::WriteInvalidateReq].onSnoop(invalidateTrans); - transitionTable[Modified][Packet::WriteInvalidateReq].onSnoop(invalidateTrans); - - if (doUpgrades) { - transitionTable[Invalid][Packet::UpgradeReq].onSnoop(nullTransition); - transitionTable[Shared][Packet::UpgradeReq].onSnoop(invalidateTrans); - } + bool hasOwned = (protocol == "mosi" || protocol == "moesi"); + bool hasExclusive = (protocol == "mesi" || protocol == "moesi"); + + if (hasOwned && !doUpgrades) { + fatal("CoherenceProtocol: ownership protocols require upgrade " + "transactions\n(write miss on owned block generates ReadExcl, " + "which will clobber dirty block)\n"); } - else if(protocol == "mesi") { - // incoming requests: specify outgoing bus request - transitionTable[Invalid][Packet::ReadReq].onRequest(Packet::ReadReq); - transitionTable[Invalid][Packet::WriteReq].onRequest(Packet::ReadExReq); - transitionTable[Shared][Packet::WriteReq].onRequest(writeToSharedCmd); - //Prefetching causes a read - transitionTable[Invalid][Packet::SoftPFReq].onRequest(Packet::ReadReq); - transitionTable[Invalid][Packet::HardPFReq].onRequest(Packet::ReadReq); - - // on response to given request: specify new state - transitionTable[Invalid][Packet::ReadResp].onResponse(Exclusive); - //It will move into shared if the shared line is asserted in the - //getNewState function - transitionTable[Invalid][Packet::ReadExResp].onResponse(Modified); - transitionTable[Shared][writeToSharedResp].onResponse(Modified); - - // bus snoop transition functions - transitionTable[Invalid][Packet::ReadReq].onSnoop(nullTransition); - transitionTable[Invalid][Packet::ReadExReq].onSnoop(nullTransition); - transitionTable[Shared][Packet::ReadReq].onSnoop(assertShared); - transitionTable[Shared][Packet::ReadExReq].onSnoop(invalidateTrans); - transitionTable[Exclusive][Packet::ReadReq].onSnoop(assertShared); - transitionTable[Exclusive][Packet::ReadExReq].onSnoop(invalidateTrans); - transitionTable[Modified][Packet::ReadExReq].onSnoop(supplyAndInvalidateTrans); - transitionTable[Modified][Packet::ReadReq].onSnoop(supplyAndGotoSharedTrans); - //Tansitions on seeing a DMA (writeInv(samelevel) or DMAInv) - transitionTable[Invalid][Packet::InvalidateReq].onSnoop(invalidateTrans); - transitionTable[Shared][Packet::InvalidateReq].onSnoop(invalidateTrans); - transitionTable[Modified][Packet::InvalidateReq].onSnoop(invalidateTrans); - transitionTable[Exclusive][Packet::InvalidateReq].onSnoop(invalidateTrans); - transitionTable[Invalid][Packet::WriteInvalidateReq].onSnoop(invalidateTrans); - transitionTable[Shared][Packet::WriteInvalidateReq].onSnoop(invalidateTrans); - transitionTable[Modified][Packet::WriteInvalidateReq].onSnoop(invalidateTrans); - transitionTable[Exclusive][Packet::WriteInvalidateReq].onSnoop(invalidateTrans); - - if (doUpgrades) { - transitionTable[Invalid][Packet::UpgradeReq].onSnoop(nullTransition); - transitionTable[Shared][Packet::UpgradeReq].onSnoop(invalidateTrans); - } + // set up a few shortcuts to save typing & visual clutter + typedef Packet P; + StateTransition (&tt)[stateMax+1][NUM_MEM_CMDS] = transitionTable; + + P::Command writeToSharedCmd = doUpgrades ? P::UpgradeReq : P::ReadExReq; + P::Command writeToSharedResp = doUpgrades ? P::UpgradeReq : P::ReadExResp; + + // Note that all transitions by default cause a panic. + // Override the valid transitions with the appropriate actions here. + + // + // ----- incoming requests: specify outgoing bus request ----- + // + tt[Invalid][P::ReadReq].onRequest(P::ReadReq); + // we only support write allocate right now + tt[Invalid][P::WriteReq].onRequest(P::ReadExReq); + tt[Shared][P::WriteReq].onRequest(writeToSharedCmd); + if (hasOwned) { + tt[Owned][P::WriteReq].onRequest(writeToSharedCmd); } - else if(protocol == "mosi") { - // incoming requests: specify outgoing bus request - transitionTable[Invalid][Packet::ReadReq].onRequest(Packet::ReadReq); - transitionTable[Invalid][Packet::WriteReq].onRequest(Packet::ReadExReq); - transitionTable[Shared][Packet::WriteReq].onRequest(writeToSharedCmd); - transitionTable[Owned][Packet::WriteReq].onRequest(writeToSharedCmd); - //Prefetching causes a read - transitionTable[Invalid][Packet::SoftPFReq].onRequest(Packet::ReadReq); - transitionTable[Invalid][Packet::HardPFReq].onRequest(Packet::ReadReq); - - // on response to given request: specify new state - transitionTable[Invalid][Packet::ReadResp].onResponse(Shared); - transitionTable[Invalid][Packet::ReadExResp].onResponse(Modified); - transitionTable[Shared][writeToSharedResp].onResponse(Modified); - transitionTable[Owned][writeToSharedResp].onResponse(Modified); - - // bus snoop transition functions - transitionTable[Invalid][Packet::ReadReq].onSnoop(nullTransition); - transitionTable[Invalid][Packet::ReadExReq].onSnoop(nullTransition); - transitionTable[Invalid][Packet::UpgradeReq].onSnoop(nullTransition); - transitionTable[Shared][Packet::ReadReq].onSnoop(assertShared); - transitionTable[Shared][Packet::ReadExReq].onSnoop(invalidateTrans); - transitionTable[Shared][Packet::UpgradeReq].onSnoop(invalidateTrans); - transitionTable[Modified][Packet::ReadExReq].onSnoop(supplyAndInvalidateTrans); - transitionTable[Modified][Packet::ReadReq].onSnoop(supplyAndGotoOwnedTrans); - transitionTable[Owned][Packet::ReadReq].onSnoop(supplyAndGotoOwnedTrans); - transitionTable[Owned][Packet::ReadExReq].onSnoop(supplyAndInvalidateTrans); - transitionTable[Owned][Packet::UpgradeReq].onSnoop(invalidateTrans); - //Tansitions on seeing a DMA (writeInv(samelevel) or DMAInv) - transitionTable[Invalid][Packet::InvalidateReq].onSnoop(invalidateTrans); - transitionTable[Shared][Packet::InvalidateReq].onSnoop(invalidateTrans); - transitionTable[Modified][Packet::InvalidateReq].onSnoop(invalidateTrans); - transitionTable[Owned][Packet::InvalidateReq].onSnoop(invalidateTrans); - transitionTable[Invalid][Packet::WriteInvalidateReq].onSnoop(invalidateTrans); - transitionTable[Shared][Packet::WriteInvalidateReq].onSnoop(invalidateTrans); - transitionTable[Modified][Packet::WriteInvalidateReq].onSnoop(invalidateTrans); - transitionTable[Owned][Packet::WriteInvalidateReq].onSnoop(invalidateTrans); + // Prefetching causes a read + tt[Invalid][P::SoftPFReq].onRequest(P::ReadReq); + tt[Invalid][P::HardPFReq].onRequest(P::ReadReq); + + // + // ----- on response to given request: specify new state ----- + // + tt[Invalid][P::ReadExResp].onResponse(Modified); + tt[Shared][writeToSharedResp].onResponse(Modified); + // Go to Exclusive state on read response if we have one (will + // move into shared if the shared line is asserted in the + // getNewState function) + // + // originally had this as: + // tt[Invalid][P::ReadResp].onResponse(hasExclusive ? Exclusive: Shared); + // ...but for some reason that caused a link error... + if (hasExclusive) { + tt[Invalid][P::ReadResp].onResponse(Exclusive); + } else { + tt[Invalid][P::ReadResp].onResponse(Shared); + } + if (hasOwned) { + tt[Owned][writeToSharedResp].onResponse(Modified); } - else if(protocol == "moesi") { - // incoming requests: specify outgoing bus request - transitionTable[Invalid][Packet::ReadReq].onRequest(Packet::ReadReq); - transitionTable[Invalid][Packet::WriteReq].onRequest(Packet::ReadExReq); - transitionTable[Shared][Packet::WriteReq].onRequest(writeToSharedCmd); - transitionTable[Owned][Packet::WriteReq].onRequest(writeToSharedCmd); - //Prefetching causes a read - transitionTable[Invalid][Packet::SoftPFReq].onRequest(Packet::ReadReq); - transitionTable[Invalid][Packet::HardPFReq].onRequest(Packet::ReadReq); - - // on response to given request: specify new state - transitionTable[Invalid][Packet::ReadResp].onResponse(Exclusive); - //It will move into shared if the shared line is asserted in the - //getNewState function - transitionTable[Invalid][Packet::ReadExResp].onResponse(Modified); - transitionTable[Shared][writeToSharedResp].onResponse(Modified); - transitionTable[Owned][writeToSharedResp].onResponse(Modified); - - // bus snoop transition functions - transitionTable[Invalid][Packet::ReadReq].onSnoop(nullTransition); - transitionTable[Invalid][Packet::ReadExReq].onSnoop(nullTransition); - transitionTable[Invalid][Packet::UpgradeReq].onSnoop(nullTransition); - transitionTable[Shared][Packet::ReadReq].onSnoop(assertShared); - transitionTable[Shared][Packet::ReadExReq].onSnoop(invalidateTrans); - transitionTable[Shared][Packet::UpgradeReq].onSnoop(invalidateTrans); - transitionTable[Exclusive][Packet::ReadReq].onSnoop(assertShared); - transitionTable[Exclusive][Packet::ReadExReq].onSnoop(invalidateTrans); - transitionTable[Modified][Packet::ReadReq].onSnoop(supplyAndGotoOwnedTrans); - transitionTable[Modified][Packet::ReadExReq].onSnoop(supplyAndInvalidateTrans); - transitionTable[Owned][Packet::ReadReq].onSnoop(supplyAndGotoOwnedTrans); - transitionTable[Owned][Packet::ReadExReq].onSnoop(supplyAndInvalidateTrans); - transitionTable[Owned][Packet::UpgradeReq].onSnoop(invalidateTrans); - //Transitions on seeing a DMA (writeInv(samelevel) or DMAInv) - transitionTable[Invalid][Packet::InvalidateReq].onSnoop(invalidateTrans); - transitionTable[Shared][Packet::InvalidateReq].onSnoop(invalidateTrans); - transitionTable[Exclusive][Packet::InvalidateReq].onSnoop(invalidateTrans); - transitionTable[Modified][Packet::InvalidateReq].onSnoop(invalidateTrans); - transitionTable[Owned][Packet::InvalidateReq].onSnoop(invalidateTrans); - transitionTable[Invalid][Packet::WriteInvalidateReq].onSnoop(invalidateTrans); - transitionTable[Shared][Packet::WriteInvalidateReq].onSnoop(invalidateTrans); - transitionTable[Exclusive][Packet::WriteInvalidateReq].onSnoop(invalidateTrans); - transitionTable[Modified][Packet::WriteInvalidateReq].onSnoop(invalidateTrans); - transitionTable[Owned][Packet::WriteInvalidateReq].onSnoop(invalidateTrans); + // + // ----- bus snoop transition functions ----- + // + tt[Invalid][P::ReadReq].onSnoop(nullTransition); + tt[Invalid][P::ReadExReq].onSnoop(nullTransition); + tt[Invalid][P::InvalidateReq].onSnoop(invalidateTrans); + tt[Invalid][P::WriteInvalidateReq].onSnoop(invalidateTrans); + tt[Shared][P::ReadReq].onSnoop(hasExclusive + ? assertShared : nullTransition); + tt[Shared][P::ReadExReq].onSnoop(invalidateTrans); + tt[Shared][P::InvalidateReq].onSnoop(invalidateTrans); + tt[Shared][P::WriteInvalidateReq].onSnoop(invalidateTrans); + if (doUpgrades) { + tt[Invalid][P::UpgradeReq].onSnoop(nullTransition); + tt[Shared][P::UpgradeReq].onSnoop(invalidateTrans); + } + tt[Modified][P::ReadExReq].onSnoop(supplyAndInvalidateTrans); + tt[Modified][P::ReadReq].onSnoop(hasOwned + ? supplyAndGotoOwnedTrans + : supplyAndGotoSharedTrans); + tt[Modified][P::InvalidateReq].onSnoop(invalidateTrans); + tt[Modified][P::WriteInvalidateReq].onSnoop(invalidateTrans); + + if (hasExclusive) { + tt[Exclusive][P::ReadReq].onSnoop(assertShared); + tt[Exclusive][P::ReadExReq].onSnoop(invalidateTrans); + tt[Exclusive][P::InvalidateReq].onSnoop(invalidateTrans); + tt[Exclusive][P::WriteInvalidateReq].onSnoop(invalidateTrans); } - else { - cerr << "CoherenceProtocol: unrecognized protocol " << protocol - << endl; - fatal(""); + if (hasOwned) { + tt[Owned][P::ReadReq].onSnoop(supplyAndGotoOwnedTrans); + tt[Owned][P::ReadExReq].onSnoop(supplyAndInvalidateTrans); + tt[Owned][P::UpgradeReq].onSnoop(invalidateTrans); + tt[Owned][P::InvalidateReq].onSnoop(invalidateTrans); + tt[Owned][P::WriteInvalidateReq].onSnoop(invalidateTrans); } + + // @todo add in hardware prefetch to this list } @@ -463,7 +386,7 @@ CoherenceProtocol::getBusCmd(Packet::Command cmdIn, CacheBlk::State state, CacheBlk::State -CoherenceProtocol::getNewState(Packet * &pkt, CacheBlk::State oldState) +CoherenceProtocol::getNewState(PacketPtr &pkt, CacheBlk::State oldState) { CacheBlk::State state = oldState & stateMask; int cmd_idx = pkt->cmdToIndex(); @@ -488,7 +411,7 @@ CoherenceProtocol::getNewState(Packet * &pkt, CacheBlk::State oldState) bool -CoherenceProtocol::handleBusRequest(BaseCache *cache, Packet * &pkt, +CoherenceProtocol::handleBusRequest(BaseCache *cache, PacketPtr &pkt, CacheBlk *blk, MSHR *mshr, CacheBlk::State & new_state) @@ -518,7 +441,7 @@ CoherenceProtocol::handleBusRequest(BaseCache *cache, Packet * &pkt, } bool -CoherenceProtocol::nullTransition(BaseCache *cache, Packet * &pkt, +CoherenceProtocol::nullTransition(BaseCache *cache, PacketPtr &pkt, CacheBlk *blk, MSHR *mshr, CacheBlk::State & new_state) { @@ -530,7 +453,7 @@ CoherenceProtocol::nullTransition(BaseCache *cache, Packet * &pkt, bool -CoherenceProtocol::invalidTransition(BaseCache *cache, Packet * &pkt, +CoherenceProtocol::invalidTransition(BaseCache *cache, PacketPtr &pkt, CacheBlk *blk, MSHR *mshr, CacheBlk::State & new_state) { diff --git a/src/mem/cache/coherence/coherence_protocol.hh b/src/mem/cache/coherence/coherence_protocol.hh index b5d7d80aa..481277523 100644 --- a/src/mem/cache/coherence/coherence_protocol.hh +++ b/src/mem/cache/coherence/coherence_protocol.hh @@ -89,7 +89,7 @@ class CoherenceProtocol : public SimObject * @param oldState The current block state. * @return The new state. */ - CacheBlk::State getNewState(Packet * &pkt, + CacheBlk::State getNewState(PacketPtr &pkt, CacheBlk::State oldState); /** @@ -101,12 +101,12 @@ class CoherenceProtocol : public SimObject * @param new_state The new coherence state of the block. * @return True if the request should be satisfied locally. */ - bool handleBusRequest(BaseCache *cache, Packet * &pkt, CacheBlk *blk, + bool handleBusRequest(BaseCache *cache, PacketPtr &pkt, CacheBlk *blk, MSHR *mshr, CacheBlk::State &new_state); protected: /** Snoop function type. */ - typedef bool (*SnoopFuncType)(BaseCache *, Packet *&, CacheBlk *, + typedef bool (*SnoopFuncType)(BaseCache *, PacketPtr &, CacheBlk *, MSHR *, CacheBlk::State&); // @@ -116,49 +116,49 @@ class CoherenceProtocol : public SimObject /** * Do nothing transition. */ - static bool nullTransition(BaseCache *, Packet *&, CacheBlk *, + static bool nullTransition(BaseCache *, PacketPtr &, CacheBlk *, MSHR *, CacheBlk::State&); /** * Invalid transition, basically panic. */ - static bool invalidTransition(BaseCache *, Packet *&, CacheBlk *, + static bool invalidTransition(BaseCache *, PacketPtr &, CacheBlk *, MSHR *, CacheBlk::State&); /** * Invalidate block, move to Invalid state. */ - static bool invalidateTrans(BaseCache *, Packet *&, CacheBlk *, + static bool invalidateTrans(BaseCache *, PacketPtr &, CacheBlk *, MSHR *, CacheBlk::State&); /** * Supply data, no state transition. */ - static bool supplyTrans(BaseCache *, Packet *&, CacheBlk *, + static bool supplyTrans(BaseCache *, PacketPtr &, CacheBlk *, MSHR *, CacheBlk::State&); /** * Supply data and go to Shared state. */ - static bool supplyAndGotoSharedTrans(BaseCache *, Packet *&, CacheBlk *, + static bool supplyAndGotoSharedTrans(BaseCache *, PacketPtr &, CacheBlk *, MSHR *, CacheBlk::State&); /** * Supply data and go to Owned state. */ - static bool supplyAndGotoOwnedTrans(BaseCache *, Packet *&, CacheBlk *, + static bool supplyAndGotoOwnedTrans(BaseCache *, PacketPtr &, CacheBlk *, MSHR *, CacheBlk::State&); /** * Invalidate block, supply data, and go to Invalid state. */ - static bool supplyAndInvalidateTrans(BaseCache *, Packet *&, CacheBlk *, + static bool supplyAndInvalidateTrans(BaseCache *, PacketPtr &, CacheBlk *, MSHR *, CacheBlk::State&); /** * Assert the shared line for a block that is shared/exclusive. */ - static bool assertShared(BaseCache *, Packet *&, CacheBlk *, + static bool assertShared(BaseCache *, PacketPtr &, CacheBlk *, MSHR *, CacheBlk::State&); /** @@ -211,31 +211,25 @@ class CoherenceProtocol : public SimObject friend class CoherenceProtocol::StateTransition; /** Mask to select status bits relevant to coherence protocol. */ - const static CacheBlk::State - stateMask = BlkValid | BlkWritable | BlkDirty; + static const int stateMask = BlkValid | BlkWritable | BlkDirty; /** The Modified (M) state. */ - const static CacheBlk::State - Modified = BlkValid | BlkWritable | BlkDirty; + static const int Modified = BlkValid | BlkWritable | BlkDirty; /** The Owned (O) state. */ - const static CacheBlk::State - Owned = BlkValid | BlkDirty; + static const int Owned = BlkValid | BlkDirty; /** The Exclusive (E) state. */ - const static CacheBlk::State - Exclusive = BlkValid | BlkWritable; + static const int Exclusive = BlkValid | BlkWritable; /** The Shared (S) state. */ - const static CacheBlk::State - Shared = BlkValid; + static const int Shared = BlkValid; /** The Invalid (I) state. */ - const static CacheBlk::State - Invalid = 0; + static const int Invalid = 0; /** * Maximum state encoding value (used to size transition lookup * table). Could be more than number of states, depends on * encoding of status bits. */ - const static int stateMax = stateMask; + static const int stateMax = stateMask; /** * The table of all possible transitions, organized by starting state and diff --git a/src/mem/cache/coherence/simple_coherence.hh b/src/mem/cache/coherence/simple_coherence.hh index a356b3ecc..5316e64b9 100644 --- a/src/mem/cache/coherence/simple_coherence.hh +++ b/src/mem/cache/coherence/simple_coherence.hh @@ -89,7 +89,7 @@ class SimpleCoherence * This policy does not forward invalidates, return NULL. * @return NULL. */ - Packet * getPacket() + PacketPtr getPacket() { return NULL; } @@ -99,7 +99,7 @@ class SimpleCoherence * @param pkt The request. * @param success True if the request was sent successfully. */ - void sendResult(Packet * &pkt, MSHR* cshr, bool success) + void sendResult(PacketPtr &pkt, MSHR* cshr, bool success) { //Don't do coherence return; @@ -112,7 +112,7 @@ class SimpleCoherence * @param current The current block state. * @return The new state. */ - CacheBlk::State getNewState(Packet * &pkt, CacheBlk::State current) + CacheBlk::State getNewState(PacketPtr &pkt, CacheBlk::State current) { return protocol->getNewState(pkt, current); } @@ -124,7 +124,7 @@ class SimpleCoherence * @param mshr The MSHR corresponding to the request, if any. * @param new_state Return the new state for the block. */ - bool handleBusRequest(Packet * &pkt, CacheBlk *blk, MSHR *mshr, + bool handleBusRequest(PacketPtr &pkt, CacheBlk *blk, MSHR *mshr, CacheBlk::State &new_state) { // assert(mshr == NULL); @@ -160,6 +160,12 @@ class SimpleCoherence bool allowFastWrites() { return false; } bool hasProtocol() { return true; } + + void propogateInvalidate(PacketPtr pkt, bool isTiming) + { + //For now we do nothing, asssumes simple coherence is top level of cache + return; + } }; #endif //__SIMPLE_COHERENCE_HH__ diff --git a/src/mem/cache/coherence/uni_coherence.cc b/src/mem/cache/coherence/uni_coherence.cc index 751de4801..19230e35b 100644 --- a/src/mem/cache/coherence/uni_coherence.cc +++ b/src/mem/cache/coherence/uni_coherence.cc @@ -40,24 +40,24 @@ UniCoherence::UniCoherence() { } -Packet * +PacketPtr UniCoherence::getPacket() { - Packet* pkt = cshrs.getReq(); + PacketPtr pkt = cshrs.getReq(); return pkt; } void -UniCoherence::sendResult(Packet * &pkt, MSHR* cshr, bool success) +UniCoherence::sendResult(PacketPtr &pkt, MSHR* cshr, bool success) { if (success) { bool unblock = cshrs.isFull(); - cshrs.markInService(cshr); +// cshrs.markInService(cshr); + cshrs.deallocate(cshr); if (!cshrs.havePending()) { cache->clearSlaveRequest(Request_Coherence); } - cshrs.deallocate(cshr); if (unblock) { //since CSHRs are always used as buffers, should always get rid of one assert(!cshrs.isFull()); @@ -71,24 +71,36 @@ UniCoherence::sendResult(Packet * &pkt, MSHR* cshr, bool success) * @todo add support for returning slave requests, not doing them here. */ bool -UniCoherence::handleBusRequest(Packet * &pkt, CacheBlk *blk, MSHR *mshr, +UniCoherence::handleBusRequest(PacketPtr &pkt, CacheBlk *blk, MSHR *mshr, CacheBlk::State &new_state) { new_state = 0; if (pkt->isInvalidate()) { - DPRINTF(Cache, "snoop inval on blk %x (blk ptr %x)\n", - pkt->getAddr(), blk); - // Forward to other caches - Packet * tmp = new Packet(pkt->req, Packet::InvalidateReq, -1); - cshrs.allocate(tmp); - cache->setSlaveRequest(Request_Coherence, curTick); - if (cshrs.isFull()) { - cache->setBlockedForSnoop(Blocked_Coherence); + DPRINTF(Cache, "snoop inval on blk %x (blk ptr %x)\n", + pkt->getAddr(), blk); + } + else if (blk) { + new_state = blk->status; + } + return false; +} + +void +UniCoherence::propogateInvalidate(PacketPtr pkt, bool isTiming) +{ + if (pkt->isInvalidate()) { + if (isTiming) { + // Forward to other caches + PacketPtr tmp = new Packet(pkt->req, Packet::InvalidateReq, -1); + cshrs.allocate(tmp); + cache->setSlaveRequest(Request_Coherence, curTick); + if (cshrs.isFull()) + cache->setBlockedForSnoop(Blocked_Coherence); } - } else { - if (blk) { - new_state = blk->status; + else { + PacketPtr tmp = new Packet(pkt->req, Packet::InvalidateReq, -1); + cache->cpuSidePort->sendAtomic(tmp); + delete tmp; } } - return false; } diff --git a/src/mem/cache/coherence/uni_coherence.hh b/src/mem/cache/coherence/uni_coherence.hh index 60da7a36e..44c752088 100644 --- a/src/mem/cache/coherence/uni_coherence.hh +++ b/src/mem/cache/coherence/uni_coherence.hh @@ -92,7 +92,7 @@ class UniCoherence * @param current The current block state. * @return The new state. */ - CacheBlk::State getNewState(Packet * &pkt, CacheBlk::State current) + CacheBlk::State getNewState(PacketPtr &pkt, CacheBlk::State current) { if (pkt->senderState) //Blocking Buffers don't get mshrs { @@ -113,14 +113,14 @@ class UniCoherence * Return outstanding invalidate to forward. * @return The next invalidate to forward to lower levels of cache. */ - Packet * getPacket(); + PacketPtr getPacket(); /** * Was the CSHR request was sent successfully? * @param pkt The request. * @param success True if the request was sent successfully. */ - void sendResult(Packet * &pkt, MSHR* cshr, bool success); + void sendResult(PacketPtr &pkt, MSHR* cshr, bool success); /** * Handle snooped bus requests. @@ -130,7 +130,7 @@ class UniCoherence * @param new_state The new coherence state of the block. * @return True if the request should be satisfied locally. */ - bool handleBusRequest(Packet * &pkt, CacheBlk *blk, MSHR *mshr, + bool handleBusRequest(PacketPtr &pkt, CacheBlk *blk, MSHR *mshr, CacheBlk::State &new_state); /** @@ -139,6 +139,8 @@ class UniCoherence bool allowFastWrites() { return true; } bool hasProtocol() { return false; } + + void propogateInvalidate(PacketPtr pkt, bool isTiming); }; #endif //__UNI_COHERENCE_HH__ diff --git a/src/mem/cache/miss/blocking_buffer.cc b/src/mem/cache/miss/blocking_buffer.cc index f7aacff89..bf741e547 100644 --- a/src/mem/cache/miss/blocking_buffer.cc +++ b/src/mem/cache/miss/blocking_buffer.cc @@ -68,7 +68,7 @@ BlockingBuffer::setPrefetcher(BasePrefetcher *_prefetcher) prefetcher = _prefetcher; } void -BlockingBuffer::handleMiss(Packet * &pkt, int blk_size, Tick time) +BlockingBuffer::handleMiss(PacketPtr &pkt, int blk_size, Tick time) { Addr blk_addr = pkt->getAddr() & ~(Addr)(blk_size - 1); if (pkt->isWrite() && (pkt->req->isUncacheable() || !writeAllocate || @@ -98,7 +98,7 @@ BlockingBuffer::handleMiss(Packet * &pkt, int blk_size, Tick time) cache->setMasterRequest(Request_MSHR, time); } -Packet * +PacketPtr BlockingBuffer::getPacket() { if (miss.pkt && !miss.inService) { @@ -108,7 +108,7 @@ BlockingBuffer::getPacket() } void -BlockingBuffer::setBusCmd(Packet * &pkt, Packet::Command cmd) +BlockingBuffer::setBusCmd(PacketPtr &pkt, Packet::Command cmd) { MSHR *mshr = (MSHR*) pkt->senderState; mshr->originalCmd = pkt->cmd; @@ -117,13 +117,13 @@ BlockingBuffer::setBusCmd(Packet * &pkt, Packet::Command cmd) } void -BlockingBuffer::restoreOrigCmd(Packet * &pkt) +BlockingBuffer::restoreOrigCmd(PacketPtr &pkt) { pkt->cmdOverride(((MSHR*)(pkt->senderState))->originalCmd); } void -BlockingBuffer::markInService(Packet * &pkt, MSHR* mshr) +BlockingBuffer::markInService(PacketPtr &pkt, MSHR* mshr) { if (!pkt->isCacheFill() && pkt->isWrite()) { // Forwarding a write/ writeback, don't need to change @@ -152,7 +152,7 @@ BlockingBuffer::markInService(Packet * &pkt, MSHR* mshr) } void -BlockingBuffer::handleResponse(Packet * &pkt, Tick time) +BlockingBuffer::handleResponse(PacketPtr &pkt, Tick time) { if (pkt->isCacheFill()) { // targets were handled in the cache tags @@ -163,7 +163,7 @@ BlockingBuffer::handleResponse(Packet * &pkt, Tick time) if (((MSHR*)(pkt->senderState))->hasTargets()) { // Should only have 1 target if we had any assert(((MSHR*)(pkt->senderState))->getNumTargets() == 1); - Packet * target = ((MSHR*)(pkt->senderState))->getTarget(); + PacketPtr target = ((MSHR*)(pkt->senderState))->getTarget(); ((MSHR*)(pkt->senderState))->popTarget(); if (pkt->isRead()) { memcpy(target->getPtr<uint8_t>(), pkt->getPtr<uint8_t>(), target->getSize()); @@ -187,7 +187,7 @@ void BlockingBuffer::squash(int threadNum) { if (miss.threadNum == threadNum) { - Packet * target = miss.getTarget(); + PacketPtr target = miss.getTarget(); miss.popTarget(); assert(0/*target->req->getThreadNum()*/ == threadNum); target = NULL; @@ -207,7 +207,7 @@ BlockingBuffer::doWriteback(Addr addr, { // Generate request Request * req = new Request(addr, size, 0); - Packet * pkt = new Packet(req, Packet::Writeback, -1); + PacketPtr pkt = new Packet(req, Packet::Writeback, -1); pkt->allocate(); if (data) { memcpy(pkt->getPtr<uint8_t>(), data, size); @@ -228,7 +228,7 @@ BlockingBuffer::doWriteback(Addr addr, void -BlockingBuffer::doWriteback(Packet * &pkt) +BlockingBuffer::doWriteback(PacketPtr &pkt) { writebacks[0/*pkt->req->getThreadNum()*/]++; diff --git a/src/mem/cache/miss/blocking_buffer.hh b/src/mem/cache/miss/blocking_buffer.hh index f7069696c..4408cfc4f 100644 --- a/src/mem/cache/miss/blocking_buffer.hh +++ b/src/mem/cache/miss/blocking_buffer.hh @@ -111,7 +111,7 @@ public: * @param blk_size The block size of the cache. * @param time The time the miss is detected. */ - void handleMiss(Packet * &pkt, int blk_size, Tick time); + void handleMiss(PacketPtr &pkt, int blk_size, Tick time); /** * Fetch the block for the given address and buffer the given target. @@ -122,7 +122,7 @@ public: * @param target The target for the fetch. */ MSHR* fetchBlock(Addr addr, int blk_size, Tick time, - Packet * &target) + PacketPtr &target) { fatal("Unimplemented"); } @@ -131,20 +131,20 @@ public: * Selects a outstanding pktuest to service. * @return The pktuest to service, NULL if none found. */ - Packet * getPacket(); + PacketPtr getPacket(); /** * Set the command to the given bus command. * @param pkt The request to update. * @param cmd The bus command to use. */ - void setBusCmd(Packet * &pkt, Packet::Command cmd); + void setBusCmd(PacketPtr &pkt, Packet::Command cmd); /** * Restore the original command in case of a bus transmission error. * @param pkt The request to reset. */ - void restoreOrigCmd(Packet * &pkt); + void restoreOrigCmd(PacketPtr &pkt); /** * Marks a pktuest as in service (sent on the bus). This can have side @@ -152,14 +152,14 @@ public: * are successfully sent. * @param pkt The request that was sent on the bus. */ - void markInService(Packet * &pkt, MSHR* mshr); + void markInService(PacketPtr &pkt, MSHR* mshr); /** * Frees the resources of the pktuest and unblock the cache. * @param pkt The request that has been satisfied. * @param time The time when the pktuest is satisfied. */ - void handleResponse(Packet * &pkt, Tick time); + void handleResponse(PacketPtr &pkt, Tick time); /** * Removes all outstanding pktuests for a given thread number. If a request @@ -223,7 +223,7 @@ public: * Perform a writeback pktuest. * @param pkt The writeback request. */ - void doWriteback(Packet * &pkt); + void doWriteback(PacketPtr &pkt); /** * Returns true if there are outstanding pktuests. @@ -239,7 +239,7 @@ public: * @param mshr The mshr to add a target to. * @param pkt The target to add. */ - void addTarget(MSHR *mshr, Packet * &pkt) + void addTarget(MSHR *mshr, PacketPtr &pkt) { fatal("Shouldn't call this on a blocking buffer."); } diff --git a/src/mem/cache/miss/miss_queue.cc b/src/mem/cache/miss/miss_queue.cc index c23b542f5..fe467a8ea 100644 --- a/src/mem/cache/miss/miss_queue.cc +++ b/src/mem/cache/miss/miss_queue.cc @@ -350,7 +350,7 @@ MissQueue::setPrefetcher(BasePrefetcher *_prefetcher) } MSHR* -MissQueue::allocateMiss(Packet * &pkt, int size, Tick time) +MissQueue::allocateMiss(PacketPtr &pkt, int size, Tick time) { MSHR* mshr = mq.allocate(pkt, size); mshr->order = order++; @@ -370,7 +370,7 @@ MissQueue::allocateMiss(Packet * &pkt, int size, Tick time) MSHR* -MissQueue::allocateWrite(Packet * &pkt, int size, Tick time) +MissQueue::allocateWrite(PacketPtr &pkt, int size, Tick time) { MSHR* mshr = wb.allocate(pkt,size); mshr->order = order++; @@ -401,7 +401,7 @@ MissQueue::allocateWrite(Packet * &pkt, int size, Tick time) * @todo Remove SW prefetches on mshr hits. */ void -MissQueue::handleMiss(Packet * &pkt, int blkSize, Tick time) +MissQueue::handleMiss(PacketPtr &pkt, int blkSize, Tick time) { // if (!cache->isTopLevel()) if (prefetchMiss) prefetcher->handleMiss(pkt, time); @@ -455,7 +455,7 @@ MissQueue::handleMiss(Packet * &pkt, int blkSize, Tick time) MSHR* MissQueue::fetchBlock(Addr addr, int blk_size, Tick time, - Packet * &target) + PacketPtr &target) { Addr blkAddr = addr & ~(Addr)(blk_size - 1); assert(mq.findMatch(addr) == NULL); @@ -469,10 +469,10 @@ MissQueue::fetchBlock(Addr addr, int blk_size, Tick time, return mshr; } -Packet * +PacketPtr MissQueue::getPacket() { - Packet * pkt = mq.getReq(); + PacketPtr pkt = mq.getReq(); if (((wb.isFull() && wb.inServiceMSHRs == 0) || !pkt || pkt->time > curTick) && wb.havePending()) { pkt = wb.getReq(); @@ -510,7 +510,7 @@ MissQueue::getPacket() } void -MissQueue::setBusCmd(Packet * &pkt, Packet::Command cmd) +MissQueue::setBusCmd(PacketPtr &pkt, Packet::Command cmd) { assert(pkt->senderState != 0); MSHR * mshr = (MSHR*)pkt->senderState; @@ -528,13 +528,13 @@ MissQueue::setBusCmd(Packet * &pkt, Packet::Command cmd) } void -MissQueue::restoreOrigCmd(Packet * &pkt) +MissQueue::restoreOrigCmd(PacketPtr &pkt) { pkt->cmd = ((MSHR*)(pkt->senderState))->originalCmd; } void -MissQueue::markInService(Packet * &pkt, MSHR* mshr) +MissQueue::markInService(PacketPtr &pkt, MSHR* mshr) { bool unblock = false; BlockedCause cause = NUM_BLOCKED_CAUSES; @@ -583,7 +583,7 @@ MissQueue::markInService(Packet * &pkt, MSHR* mshr) void -MissQueue::handleResponse(Packet * &pkt, Tick time) +MissQueue::handleResponse(PacketPtr &pkt, Tick time) { MSHR* mshr = (MSHR*)pkt->senderState; if (((MSHR*)(pkt->senderState))->originalCmd == Packet::HardPFReq) { @@ -632,7 +632,7 @@ MissQueue::handleResponse(Packet * &pkt, Tick time) if (mshr->hasTargets() && pkt->req->isUncacheable()) { // Should only have 1 target if we had any assert(num_targets == 1); - Packet * target = mshr->getTarget(); + PacketPtr target = mshr->getTarget(); mshr->popTarget(); if (pkt->isRead()) { memcpy(target->getPtr<uint8_t>(), pkt->getPtr<uint8_t>(), @@ -645,7 +645,7 @@ MissQueue::handleResponse(Packet * &pkt, Tick time) //Must be a no_allocate with possibly more than one target assert(mshr->pkt->isNoAllocate()); while (mshr->hasTargets()) { - Packet * target = mshr->getTarget(); + PacketPtr target = mshr->getTarget(); mshr->popTarget(); if (pkt->isRead()) { memcpy(target->getPtr<uint8_t>(), pkt->getPtr<uint8_t>(), @@ -721,7 +721,7 @@ MissQueue::doWriteback(Addr addr, { // Generate request Request * req = new Request(addr, size, 0); - Packet * pkt = new Packet(req, Packet::Writeback, -1); + PacketPtr pkt = new Packet(req, Packet::Writeback, -1); pkt->allocate(); if (data) { memcpy(pkt->getPtr<uint8_t>(), data, size); @@ -739,7 +739,7 @@ MissQueue::doWriteback(Addr addr, void -MissQueue::doWriteback(Packet * &pkt) +MissQueue::doWriteback(PacketPtr &pkt) { writebacks[0/*pkt->req->getThreadNum()*/]++; allocateWrite(pkt, 0, curTick); diff --git a/src/mem/cache/miss/miss_queue.hh b/src/mem/cache/miss/miss_queue.hh index 179638d2b..2e04802fb 100644 --- a/src/mem/cache/miss/miss_queue.hh +++ b/src/mem/cache/miss/miss_queue.hh @@ -169,7 +169,7 @@ class MissQueue * @param time The time the miss occurs. * @return A pointer to the new MSHR. */ - MSHR* allocateMiss(Packet * &pkt, int size, Tick time); + MSHR* allocateMiss(PacketPtr &pkt, int size, Tick time); /** * Allocate a new WriteBuffer to handle the provided write. @@ -178,7 +178,7 @@ class MissQueue * @param time The time the write occurs. * @return A pointer to the new write buffer. */ - MSHR* allocateWrite(Packet * &pkt, int size, Tick time); + MSHR* allocateWrite(PacketPtr &pkt, int size, Tick time); public: /** @@ -218,7 +218,7 @@ class MissQueue * @param blk_size The block size of the cache. * @param time The time the miss is detected. */ - void handleMiss(Packet * &pkt, int blk_size, Tick time); + void handleMiss(PacketPtr &pkt, int blk_size, Tick time); /** * Fetch the block for the given address and buffer the given target. @@ -229,26 +229,26 @@ class MissQueue * @param target The target for the fetch. */ MSHR* fetchBlock(Addr addr, int blk_size, Tick time, - Packet * &target); + PacketPtr &target); /** * Selects a outstanding pktuest to service. * @return The pktuest to service, NULL if none found. */ - Packet * getPacket(); + PacketPtr getPacket(); /** * Set the command to the given bus command. * @param pkt The request to update. * @param cmd The bus command to use. */ - void setBusCmd(Packet * &pkt, Packet::Command cmd); + void setBusCmd(PacketPtr &pkt, Packet::Command cmd); /** * Restore the original command in case of a bus transmission error. * @param pkt The request to reset. */ - void restoreOrigCmd(Packet * &pkt); + void restoreOrigCmd(PacketPtr &pkt); /** * Marks a pktuest as in service (sent on the bus). This can have side @@ -256,14 +256,14 @@ class MissQueue * are successfully sent. * @param pkt The request that was sent on the bus. */ - void markInService(Packet * &pkt, MSHR* mshr); + void markInService(PacketPtr &pkt, MSHR* mshr); /** * Collect statistics and free resources of a satisfied pktuest. * @param pkt The request that has been satisfied. * @param time The time when the pktuest is satisfied. */ - void handleResponse(Packet * &pkt, Tick time); + void handleResponse(PacketPtr &pkt, Tick time); /** * Removes all outstanding pktuests for a given thread number. If a request @@ -316,7 +316,7 @@ class MissQueue * Perform the given writeback pktuest. * @param pkt The writeback request. */ - void doWriteback(Packet * &pkt); + void doWriteback(PacketPtr &pkt); /** * Returns true if there are outstanding pktuests. @@ -329,7 +329,7 @@ class MissQueue * @param mshr The mshr to add a target to. * @param pkt The target to add. */ - void addTarget(MSHR *mshr, Packet * &pkt) + void addTarget(MSHR *mshr, PacketPtr &pkt) { mq.allocateTarget(mshr, pkt); } diff --git a/src/mem/cache/miss/mshr.cc b/src/mem/cache/miss/mshr.cc index 455798f15..fc520b4b4 100644 --- a/src/mem/cache/miss/mshr.cc +++ b/src/mem/cache/miss/mshr.cc @@ -55,7 +55,7 @@ MSHR::MSHR() void MSHR::allocate(Packet::Command cmd, Addr _addr, int size, - Packet * &target) + PacketPtr &target) { addr = _addr; if (target) @@ -85,7 +85,7 @@ MSHR::allocate(Packet::Command cmd, Addr _addr, int size, * @todo When we have a "global" data flag, might want to copy data here. */ void -MSHR::allocateAsBuffer(Packet * &target) +MSHR::allocateAsBuffer(PacketPtr &target) { addr = target->getAddr(); threadNum = 0/*target->req->getThreadNum()*/; @@ -111,13 +111,13 @@ MSHR::deallocate() * Adds a target to an MSHR */ void -MSHR::allocateTarget(Packet * &target) +MSHR::allocateTarget(PacketPtr &target) { //If we append an invalidate and we issued a read to the bus, //but now have some pending writes, we need to move //the invalidate to before the first non-read if (inService && pkt->isRead() && target->isInvalidate()) { - std::list<Packet *> temp; + std::list<PacketPtr> temp; while (!targets.empty()) { if (!targets.front()->isRead()) break; diff --git a/src/mem/cache/miss/mshr.hh b/src/mem/cache/miss/mshr.hh index 028259b35..d92aa8a85 100644 --- a/src/mem/cache/miss/mshr.hh +++ b/src/mem/cache/miss/mshr.hh @@ -49,9 +49,9 @@ class MSHR; class MSHR { public: /** Defines the Data structure of the MSHR targetlist. */ - typedef std::list<Packet *> TargetList; + typedef std::list<PacketPtr> TargetList; /** Target list iterator. */ - typedef std::list<Packet *>::iterator TargetListIterator; + typedef std::list<PacketPtr>::iterator TargetListIterator; /** A list of MSHRs. */ typedef std::list<MSHR *> List; /** MSHR list iterator. */ @@ -68,7 +68,7 @@ class MSHR { /** Thread number of the miss. */ int threadNum; /** The pktuest that is forwarded to the next level of the hierarchy. */ - Packet * pkt; + PacketPtr pkt; /** The number of currently allocated targets. */ short ntargets; /** The original pktuesting command. */ @@ -101,13 +101,13 @@ public: * @param pkt The original miss. */ void allocate(Packet::Command cmd, Addr addr, int size, - Packet * &pkt); + PacketPtr &pkt); /** * Allocate this MSHR as a buffer for the given pktuest. * @param target The memory pktuest to buffer. */ - void allocateAsBuffer(Packet * &target); + void allocateAsBuffer(PacketPtr &target); /** * Mark this MSHR as free. @@ -118,7 +118,7 @@ public: * Add a pktuest to the list of targets. * @param target The target. */ - void allocateTarget(Packet * &target); + void allocateTarget(PacketPtr &target); /** A simple constructor. */ MSHR(); @@ -147,7 +147,7 @@ public: * Returns a reference to the first target. * @return A pointer to the first target. */ - Packet * getTarget() + PacketPtr getTarget() { return targets.front(); } diff --git a/src/mem/cache/miss/mshr_queue.cc b/src/mem/cache/miss/mshr_queue.cc index 777443e5f..d3a7a7933 100644 --- a/src/mem/cache/miss/mshr_queue.cc +++ b/src/mem/cache/miss/mshr_queue.cc @@ -88,7 +88,7 @@ MSHRQueue::findMatches(Addr addr, vector<MSHR*>& matches) const } MSHR* -MSHRQueue::findPending(Packet * &pkt) const +MSHRQueue::findPending(PacketPtr &pkt) const { MSHR::ConstIterator i = pendingList.begin(); MSHR::ConstIterator end = pendingList.end(); @@ -108,7 +108,7 @@ MSHRQueue::findPending(Packet * &pkt) const } MSHR* -MSHRQueue::allocate(Packet * &pkt, int size) +MSHRQueue::allocate(PacketPtr &pkt, int size) { Addr aligned_addr = pkt->getAddr() & ~((Addr)size - 1); assert(!freeList.empty()); @@ -131,7 +131,7 @@ MSHRQueue::allocate(Packet * &pkt, int size) } MSHR* -MSHRQueue::allocateFetch(Addr addr, int size, Packet * &target) +MSHRQueue::allocateFetch(Addr addr, int size, PacketPtr &target) { MSHR *mshr = freeList.front(); assert(mshr->getNumTargets() == 0); @@ -150,7 +150,7 @@ MSHRQueue::allocateTargetList(Addr addr, int size) MSHR *mshr = freeList.front(); assert(mshr->getNumTargets() == 0); freeList.pop_front(); - Packet * dummy; + PacketPtr dummy; mshr->allocate(Packet::ReadReq, addr, size, dummy); mshr->allocIter = allocatedList.insert(allocatedList.end(), mshr); mshr->inService = true; @@ -237,7 +237,7 @@ MSHRQueue::squash(int threadNum) MSHR *mshr = *i; if (mshr->threadNum == threadNum) { while (mshr->hasTargets()) { - Packet * target = mshr->getTarget(); + PacketPtr target = mshr->getTarget(); mshr->popTarget(); assert(0/*target->req->getThreadNum()*/ == threadNum); diff --git a/src/mem/cache/miss/mshr_queue.hh b/src/mem/cache/miss/mshr_queue.hh index ea5f101b7..30397d9a0 100644 --- a/src/mem/cache/miss/mshr_queue.hh +++ b/src/mem/cache/miss/mshr_queue.hh @@ -107,7 +107,7 @@ class MSHRQueue { * @param pkt The request to find. * @return A pointer to the earliest matching MSHR. */ - MSHR* findPending(Packet * &pkt) const; + MSHR* findPending(PacketPtr &pkt) const; /** * Allocates a new MSHR for the pktuest and size. This places the request @@ -118,7 +118,7 @@ class MSHRQueue { * * @pre There are free MSHRs. */ - MSHR* allocate(Packet * &pkt, int size = 0); + MSHR* allocate(PacketPtr &pkt, int size = 0); /** * Allocate a read pktuest for the given address, and places the given @@ -129,7 +129,7 @@ class MSHRQueue { * @param target The first target for the pktuest. * @return Pointer to the new MSHR. */ - MSHR* allocateFetch(Addr addr, int size, Packet * &target); + MSHR* allocateFetch(Addr addr, int size, PacketPtr &target); /** * Allocate a target list for the given address. @@ -153,7 +153,7 @@ class MSHRQueue { * @param mshr The MSHR to allocate the target to. * @param pkt The target request. */ - void allocateTarget(MSHR* mshr, Packet * &pkt) + void allocateTarget(MSHR* mshr, PacketPtr &pkt) { mshr->allocateTarget(pkt); allocatedTargets += 1; @@ -216,7 +216,7 @@ class MSHRQueue { * Returns the pktuest at the head of the pendingList. * @return The next pktuest to service. */ - Packet * getReq() const + PacketPtr getReq() const { if (pendingList.empty()) { return NULL; diff --git a/src/mem/cache/prefetch/base_prefetcher.cc b/src/mem/cache/prefetch/base_prefetcher.cc index 5e50c48bd..a1388fad6 100644 --- a/src/mem/cache/prefetch/base_prefetcher.cc +++ b/src/mem/cache/prefetch/base_prefetcher.cc @@ -102,7 +102,7 @@ BasePrefetcher::regStats(const std::string &name) ; } -Packet * +PacketPtr BasePrefetcher::getPacket() { DPRINTF(HWPrefetch, "%s:Requesting a hw_pf to issue\n", cache->name()); @@ -112,7 +112,7 @@ BasePrefetcher::getPacket() return NULL; } - Packet * pkt; + PacketPtr pkt; bool keepTrying = false; do { pkt = *pf.begin(); @@ -131,7 +131,7 @@ BasePrefetcher::getPacket() } void -BasePrefetcher::handleMiss(Packet * &pkt, Tick time) +BasePrefetcher::handleMiss(PacketPtr &pkt, Tick time) { if (!pkt->req->isUncacheable() && !(pkt->req->isInstRead() && only_data)) { @@ -139,7 +139,7 @@ BasePrefetcher::handleMiss(Packet * &pkt, Tick time) Addr blkAddr = pkt->getAddr() & ~(Addr)(blkSize-1); //Check if miss is in pfq, if so remove it - std::list<Packet *>::iterator iter = inPrefetch(blkAddr); + std::list<PacketPtr>::iterator iter = inPrefetch(blkAddr); if (iter != pf.end()) { DPRINTF(HWPrefetch, "%s:Saw a miss to a queued prefetch, removing it\n", cache->name()); pfRemovedMSHR++; @@ -179,7 +179,7 @@ BasePrefetcher::handleMiss(Packet * &pkt, Tick time) pfIdentified++; //create a prefetch memreq Request * prefetchReq = new Request(*addr, blkSize, 0); - Packet * prefetch; + PacketPtr prefetch; prefetch = new Packet(prefetchReq, Packet::HardPFReq, -1); prefetch->allocate(); prefetch->req->setThreadContext(pkt->req->getCpuNum(), @@ -233,11 +233,11 @@ BasePrefetcher::handleMiss(Packet * &pkt, Tick time) } } -std::list<Packet *>::iterator +std::list<PacketPtr>::iterator BasePrefetcher::inPrefetch(Addr address) { //Guaranteed to only be one match, we always check before inserting - std::list<Packet *>::iterator iter; + std::list<PacketPtr>::iterator iter; for (iter=pf.begin(); iter != pf.end(); iter++) { if (((*iter)->getAddr() & ~(Addr)(blkSize-1)) == address) { return iter; diff --git a/src/mem/cache/prefetch/base_prefetcher.hh b/src/mem/cache/prefetch/base_prefetcher.hh index d7ea41961..781d3ab09 100644 --- a/src/mem/cache/prefetch/base_prefetcher.hh +++ b/src/mem/cache/prefetch/base_prefetcher.hh @@ -45,7 +45,7 @@ class BasePrefetcher protected: /** The Prefetch Queue. */ - std::list<Packet *> pf; + std::list<PacketPtr> pf; // PARAMETERS @@ -93,24 +93,24 @@ class BasePrefetcher void setCache(BaseCache *_cache); - void handleMiss(Packet * &pkt, Tick time); + void handleMiss(PacketPtr &pkt, Tick time); - Packet * getPacket(); + PacketPtr getPacket(); bool havePending() { return !pf.empty(); } - virtual void calculatePrefetch(Packet * &pkt, + virtual void calculatePrefetch(PacketPtr &pkt, std::list<Addr> &addresses, std::list<Tick> &delays) = 0; - virtual bool inCache(Packet * &pkt) = 0; + virtual bool inCache(PacketPtr &pkt) = 0; virtual bool inMissQueue(Addr address) = 0; - std::list<Packet *>::iterator inPrefetch(Addr address); + std::list<PacketPtr>::iterator inPrefetch(Addr address); }; diff --git a/src/mem/cache/prefetch/ghb_prefetcher.hh b/src/mem/cache/prefetch/ghb_prefetcher.hh index c22b763d1..14f5747df 100644 --- a/src/mem/cache/prefetch/ghb_prefetcher.hh +++ b/src/mem/cache/prefetch/ghb_prefetcher.hh @@ -75,7 +75,7 @@ class GHBPrefetcher : public Prefetcher<TagStore, Buffering> ~GHBPrefetcher() {} - void calculatePrefetch(Packet * &pkt, std::list<Addr> &addresses, + void calculatePrefetch(PacketPtr &pkt, std::list<Addr> &addresses, std::list<Tick> &delays) { Addr blkAddr = pkt->getAddr() & ~(Addr)(this->blkSize-1); diff --git a/src/mem/cache/prefetch/stride_prefetcher.hh b/src/mem/cache/prefetch/stride_prefetcher.hh index 4a8ee7de4..d6fb8ab66 100644 --- a/src/mem/cache/prefetch/stride_prefetcher.hh +++ b/src/mem/cache/prefetch/stride_prefetcher.hh @@ -92,7 +92,7 @@ class StridePrefetcher : public Prefetcher<TagStore, Buffering> ~StridePrefetcher() {} - void calculatePrefetch(Packet * &pkt, std::list<Addr> &addresses, + void calculatePrefetch(PacketPtr &pkt, std::list<Addr> &addresses, std::list<Tick> &delays) { // Addr blkAddr = pkt->paddr & ~(Addr)(this->blkSize-1); diff --git a/src/mem/cache/prefetch/tagged_prefetcher.hh b/src/mem/cache/prefetch/tagged_prefetcher.hh index 17f500dd8..b61e57dcc 100644 --- a/src/mem/cache/prefetch/tagged_prefetcher.hh +++ b/src/mem/cache/prefetch/tagged_prefetcher.hh @@ -64,7 +64,7 @@ class TaggedPrefetcher : public Prefetcher<TagStore, Buffering> ~TaggedPrefetcher() {} - void calculatePrefetch(Packet * &pkt, std::list<Addr> &addresses, + void calculatePrefetch(PacketPtr &pkt, std::list<Addr> &addresses, std::list<Tick> &delays); }; diff --git a/src/mem/cache/prefetch/tagged_prefetcher_impl.hh b/src/mem/cache/prefetch/tagged_prefetcher_impl.hh index e554b3cec..a18de4571 100644 --- a/src/mem/cache/prefetch/tagged_prefetcher_impl.hh +++ b/src/mem/cache/prefetch/tagged_prefetcher_impl.hh @@ -50,7 +50,7 @@ TaggedPrefetcher(int size, bool pageStop, bool serialSquash, template <class TagStore, class Buffering> void TaggedPrefetcher<TagStore, Buffering>:: -calculatePrefetch(Packet * &pkt, std::list<Addr> &addresses, +calculatePrefetch(PacketPtr &pkt, std::list<Addr> &addresses, std::list<Tick> &delays) { Addr blkAddr = pkt->getAddr() & ~(Addr)(this->blkSize-1); diff --git a/src/mem/cache/tags/fa_lru.cc b/src/mem/cache/tags/fa_lru.cc index 784ba1311..a58ddaff8 100644 --- a/src/mem/cache/tags/fa_lru.cc +++ b/src/mem/cache/tags/fa_lru.cc @@ -203,7 +203,7 @@ FALRU::findBlock(Addr addr, int &lat, int *inCache) } FALRUBlk* -FALRU::findBlock(Packet * &pkt, int &lat, int *inCache) +FALRU::findBlock(PacketPtr &pkt, int &lat, int *inCache) { Addr addr = pkt->getAddr(); @@ -256,7 +256,7 @@ FALRU::findBlock(Addr addr) const } FALRUBlk* -FALRU::findReplacement(Packet * &pkt, PacketList &writebacks, +FALRU::findReplacement(PacketPtr &pkt, PacketList &writebacks, BlkList &compress_blocks) { FALRUBlk * blk = tail; diff --git a/src/mem/cache/tags/fa_lru.hh b/src/mem/cache/tags/fa_lru.hh index 0fc54902b..2db89d603 100644 --- a/src/mem/cache/tags/fa_lru.hh +++ b/src/mem/cache/tags/fa_lru.hh @@ -198,7 +198,7 @@ public: * @param inCache The FALRUBlk::inCache flags. * @return Pointer to the cache block. */ - FALRUBlk* findBlock(Packet * &pkt, int &lat, int *inCache = 0); + FALRUBlk* findBlock(PacketPtr &pkt, int &lat, int *inCache = 0); /** * Find the block in the cache, do not update the replacement data. @@ -215,7 +215,7 @@ public: * @param compress_blocks List of blocks to compress, for adaptive comp. * @return The block to place the replacement in. */ - FALRUBlk* findReplacement(Packet * &pkt, PacketList & writebacks, + FALRUBlk* findReplacement(PacketPtr &pkt, PacketList & writebacks, BlkList &compress_blocks); /** diff --git a/src/mem/cache/tags/iic.cc b/src/mem/cache/tags/iic.cc index bf1d9ece4..f4e870659 100644 --- a/src/mem/cache/tags/iic.cc +++ b/src/mem/cache/tags/iic.cc @@ -285,7 +285,7 @@ IIC::findBlock(Addr addr, int &lat) } IICTag* -IIC::findBlock(Packet * &pkt, int &lat) +IIC::findBlock(PacketPtr &pkt, int &lat) { Addr addr = pkt->getAddr(); @@ -362,7 +362,7 @@ IIC::findBlock(Addr addr) const IICTag* -IIC::findReplacement(Packet * &pkt, PacketList &writebacks, +IIC::findReplacement(PacketPtr &pkt, PacketList &writebacks, BlkList &compress_blocks) { DPRINTF(IIC, "Finding Replacement for %x\n", pkt->getAddr()); @@ -423,7 +423,7 @@ IIC::freeReplacementBlock(PacketList & writebacks) tag_ptr->refCount = 0; if (tag_ptr->isModified()) { -/* Packet * writeback = +/* PacketPtr writeback = buildWritebackReq(regenerateBlkAddr(tag_ptr->tag, 0), tag_ptr->req->asid, tag_ptr->xc, blkSize, tag_ptr->data, @@ -431,7 +431,7 @@ IIC::freeReplacementBlock(PacketList & writebacks) */ Request *writebackReq = new Request(regenerateBlkAddr(tag_ptr->tag, 0), blkSize, 0); - Packet *writeback = new Packet(writebackReq, Packet::Writeback, -1); + PacketPtr writeback = new Packet(writebackReq, Packet::Writeback, -1); writeback->allocate(); memcpy(writeback->getPtr<uint8_t>(), tag_ptr->data, blkSize); diff --git a/src/mem/cache/tags/iic.hh b/src/mem/cache/tags/iic.hh index 905d480c5..92bd6da1d 100644 --- a/src/mem/cache/tags/iic.hh +++ b/src/mem/cache/tags/iic.hh @@ -458,7 +458,7 @@ class IIC : public BaseTags * @param lat The access latency. * @return A pointer to the block found, if any. */ - IICTag* findBlock(Packet * &pkt, int &lat); + IICTag* findBlock(PacketPtr &pkt, int &lat); /** * Find the block, do not update the replacement data. @@ -475,7 +475,7 @@ class IIC : public BaseTags * @param compress_blocks List of blocks to compress, for adaptive comp. * @return The block to place the replacement in. */ - IICTag* findReplacement(Packet * &pkt, PacketList &writebacks, + IICTag* findReplacement(PacketPtr &pkt, PacketList &writebacks, BlkList &compress_blocks); /** diff --git a/src/mem/cache/tags/lru.cc b/src/mem/cache/tags/lru.cc index a9ae049c3..31d29aae6 100644 --- a/src/mem/cache/tags/lru.cc +++ b/src/mem/cache/tags/lru.cc @@ -184,7 +184,7 @@ LRU::findBlock(Addr addr, int &lat) } LRUBlk* -LRU::findBlock(Packet * &pkt, int &lat) +LRU::findBlock(PacketPtr &pkt, int &lat) { Addr addr = pkt->getAddr(); @@ -215,7 +215,7 @@ LRU::findBlock(Addr addr) const } LRUBlk* -LRU::findReplacement(Packet * &pkt, PacketList &writebacks, +LRU::findReplacement(PacketPtr &pkt, PacketList &writebacks, BlkList &compress_blocks) { unsigned set = extractSet(pkt->getAddr()); @@ -246,6 +246,7 @@ LRU::invalidateBlk(Addr addr) if (blk) { blk->status = 0; blk->isTouched = false; + blk->clearLoadLocks(); tagsInUse--; } } diff --git a/src/mem/cache/tags/lru.hh b/src/mem/cache/tags/lru.hh index 9f0a05ee8..fed688283 100644 --- a/src/mem/cache/tags/lru.hh +++ b/src/mem/cache/tags/lru.hh @@ -174,7 +174,7 @@ public: * @param lat The access latency. * @return Pointer to the cache block if found. */ - LRUBlk* findBlock(Packet * &pkt, int &lat); + LRUBlk* findBlock(PacketPtr &pkt, int &lat); /** * Finds the given address in the cache and update replacement data. @@ -201,7 +201,7 @@ public: * @param compress_blocks List of blocks to compress, for adaptive comp. * @return The block to place the replacement in. */ - LRUBlk* findReplacement(Packet * &pkt, PacketList &writebacks, + LRUBlk* findReplacement(PacketPtr &pkt, PacketList &writebacks, BlkList &compress_blocks); /** diff --git a/src/mem/cache/tags/split.cc b/src/mem/cache/tags/split.cc index cad18e885..bc74f0e0f 100644 --- a/src/mem/cache/tags/split.cc +++ b/src/mem/cache/tags/split.cc @@ -267,7 +267,7 @@ Split::probe(Addr addr) const } SplitBlk* -Split::findBlock(Packet * &pkt, int &lat) +Split::findBlock(PacketPtr &pkt, int &lat) { Addr aligned = blkAlign(pkt->getAddr()); @@ -350,7 +350,7 @@ Split::findBlock(Addr addr) const } SplitBlk* -Split::findReplacement(Packet * &pkt, PacketList &writebacks, +Split::findReplacement(PacketPtr &pkt, PacketList &writebacks, BlkList &compress_blocks) { SplitBlk *blk; diff --git a/src/mem/cache/tags/split.hh b/src/mem/cache/tags/split.hh index 708058e96..748f6fb25 100644 --- a/src/mem/cache/tags/split.hh +++ b/src/mem/cache/tags/split.hh @@ -207,7 +207,7 @@ class Split : public BaseTags * @param lat The access latency. * @return Pointer to the cache block if found. */ - SplitBlk* findBlock(Packet * &pkt, int &lat); + SplitBlk* findBlock(PacketPtr &pkt, int &lat); /** * Finds the given address in the cache, do not update replacement data. @@ -224,7 +224,7 @@ class Split : public BaseTags * @param compress_blocks List of blocks to compress, for adaptive comp. * @return The block to place the replacement in. */ - SplitBlk* findReplacement(Packet * &pkt, PacketList &writebacks, + SplitBlk* findReplacement(PacketPtr &pkt, PacketList &writebacks, BlkList &compress_blocks); diff --git a/src/mem/cache/tags/split_lifo.cc b/src/mem/cache/tags/split_lifo.cc index 4e9375070..302e2aaeb 100644 --- a/src/mem/cache/tags/split_lifo.cc +++ b/src/mem/cache/tags/split_lifo.cc @@ -255,7 +255,7 @@ SplitLIFO::findBlock(Addr addr, int &lat) } SplitBlk* -SplitLIFO::findBlock(Packet * &pkt, int &lat) +SplitLIFO::findBlock(PacketPtr &pkt, int &lat) { Addr addr = pkt->getAddr(); @@ -291,7 +291,7 @@ SplitLIFO::findBlock(Addr addr) const } SplitBlk* -SplitLIFO::findReplacement(Packet * &pkt, PacketList &writebacks, +SplitLIFO::findReplacement(PacketPtr &pkt, PacketList &writebacks, BlkList &compress_blocks) { unsigned set = extractSet(pkt->getAddr()); diff --git a/src/mem/cache/tags/split_lifo.hh b/src/mem/cache/tags/split_lifo.hh index ddc7fdeec..6c3befe37 100644 --- a/src/mem/cache/tags/split_lifo.hh +++ b/src/mem/cache/tags/split_lifo.hh @@ -207,7 +207,7 @@ public: * @param lat The access latency. * @return Pointer to the cache block if found. */ - SplitBlk* findBlock(Packet * &pkt, int &lat); + SplitBlk* findBlock(PacketPtr &pkt, int &lat); /** * Finds the given address in the cache, do not update replacement data. @@ -224,7 +224,7 @@ public: * @param compress_blocks List of blocks to compress, for adaptive comp. * @return The block to place the replacement in. */ - SplitBlk* findReplacement(Packet * &pkt, PacketList &writebacks, + SplitBlk* findReplacement(PacketPtr &pkt, PacketList &writebacks, BlkList &compress_blocks); /** diff --git a/src/mem/cache/tags/split_lru.cc b/src/mem/cache/tags/split_lru.cc index 4aba1c37f..11c9a5d64 100644 --- a/src/mem/cache/tags/split_lru.cc +++ b/src/mem/cache/tags/split_lru.cc @@ -203,7 +203,7 @@ SplitLRU::findBlock(Addr addr, int &lat) } SplitBlk* -SplitLRU::findBlock(Packet * &pkt, int &lat) +SplitLRU::findBlock(PacketPtr &pkt, int &lat) { Addr addr = pkt->getAddr(); @@ -234,7 +234,7 @@ SplitLRU::findBlock(Addr addr) const } SplitBlk* -SplitLRU::findReplacement(Packet * &pkt, PacketList &writebacks, +SplitLRU::findReplacement(PacketPtr &pkt, PacketList &writebacks, BlkList &compress_blocks) { unsigned set = extractSet(pkt->getAddr()); diff --git a/src/mem/cache/tags/split_lru.hh b/src/mem/cache/tags/split_lru.hh index 71f921177..6160d59e5 100644 --- a/src/mem/cache/tags/split_lru.hh +++ b/src/mem/cache/tags/split_lru.hh @@ -190,7 +190,7 @@ public: * @param lat The access latency. * @return Pointer to the cache block if found. */ - SplitBlk* findBlock(Packet * &pkt, int &lat); + SplitBlk* findBlock(PacketPtr &pkt, int &lat); /** * Finds the given address in the cache, do not update replacement data. @@ -207,7 +207,7 @@ public: * @param compress_blocks List of blocks to compress, for adaptive comp. * @return The block to place the replacement in. */ - SplitBlk* findReplacement(Packet * &pkt, PacketList &writebacks, + SplitBlk* findReplacement(PacketPtr &pkt, PacketList &writebacks, BlkList &compress_blocks); /** |