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-rw-r--r--src/mem/cache/cache_impl.hh3
-rw-r--r--src/mem/cache/prefetch/Prefetcher.py7
-rw-r--r--src/mem/cache/prefetch/base.cc8
-rw-r--r--src/mem/cache/prefetch/base.hh8
-rw-r--r--src/mem/cache/prefetch/ghb.cc17
-rw-r--r--src/mem/cache/prefetch/ghb.hh6
-rw-r--r--src/mem/cache/prefetch/stride.cc11
-rw-r--r--src/mem/cache/tags/iic.cc2
8 files changed, 32 insertions, 30 deletions
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index 16b5148dc..fbab8465e 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -1006,7 +1006,8 @@ Cache<TagStore>::writebackBlk(BlkType *blk)
writebacks[0/*pkt->req->threadId()*/]++;
Request *writebackReq =
- new Request(tags->regenerateBlkAddr(blk->tag, blk->set), blkSize, 0);
+ new Request(tags->regenerateBlkAddr(blk->tag, blk->set), blkSize, 0,
+ Request::wbMasterId);
PacketPtr writeback = new Packet(writebackReq, MemCmd::Writeback, -1);
if (blk->isWritable()) {
writeback->setSupplyExclusive();
diff --git a/src/mem/cache/prefetch/Prefetcher.py b/src/mem/cache/prefetch/Prefetcher.py
index c2c17fa96..fa926e235 100644
--- a/src/mem/cache/prefetch/Prefetcher.py
+++ b/src/mem/cache/prefetch/Prefetcher.py
@@ -1,5 +1,7 @@
from m5.SimObject import SimObject
from m5.params import *
+from m5.proxy import *
+
class BasePrefetcher(SimObject):
type = 'BasePrefetcher'
abstract = True
@@ -13,10 +15,11 @@ class BasePrefetcher(SimObject):
"Degree of the prefetch depth")
latency = Param.Latency('10t',
"Latency of the prefetcher")
- use_cpu_id = Param.Bool(True,
- "Use the CPU ID to separate calculations of prefetches")
+ use_master_id = Param.Bool(True,
+ "Use the master id to separate calculations of prefetches")
data_accesses_only = Param.Bool(False,
"Only prefetch on data not on instruction accesses")
+ sys = Param.System(Parent.any, "System this device belongs to")
class GHBPrefetcher(BasePrefetcher):
type = 'GHBPrefetcher'
diff --git a/src/mem/cache/prefetch/base.cc b/src/mem/cache/prefetch/base.cc
index 834787db6..467550823 100644
--- a/src/mem/cache/prefetch/base.cc
+++ b/src/mem/cache/prefetch/base.cc
@@ -42,11 +42,13 @@
#include "mem/cache/prefetch/base.hh"
#include "mem/cache/base.hh"
#include "mem/request.hh"
+#include "sim/system.hh"
BasePrefetcher::BasePrefetcher(const Params *p)
: SimObject(p), size(p->size), latency(p->latency), degree(p->degree),
- useContextId(p->use_cpu_id), pageStop(!p->cross_pages),
- serialSquash(p->serial_squash), onlyData(p->data_accesses_only)
+ useMasterId(p->use_master_id), pageStop(!p->cross_pages),
+ serialSquash(p->serial_squash), onlyData(p->data_accesses_only),
+ system(p->sys), masterId(system->getMasterId(name()))
{
}
@@ -230,7 +232,7 @@ BasePrefetcher::notify(PacketPtr &pkt, Tick time)
}
// create a prefetch memreq
- Request *prefetchReq = new Request(*addrIter, blkSize, 0);
+ Request *prefetchReq = new Request(*addrIter, blkSize, 0, masterId);
PacketPtr prefetch =
new Packet(prefetchReq, MemCmd::HardPFReq, Packet::Broadcast);
prefetch->allocate();
diff --git a/src/mem/cache/prefetch/base.hh b/src/mem/cache/prefetch/base.hh
index ead163215..1517be50c 100644
--- a/src/mem/cache/prefetch/base.hh
+++ b/src/mem/cache/prefetch/base.hh
@@ -70,7 +70,7 @@ class BasePrefetcher : public SimObject
unsigned degree;
/** If patterns should be found per context id */
- bool useContextId;
+ bool useMasterId;
/** Do we prefetch across page boundaries. */
bool pageStop;
@@ -80,6 +80,12 @@ class BasePrefetcher : public SimObject
/** Do we prefetch on only data reads, or on inst reads as well. */
bool onlyData;
+ /** System we belong to */
+ System* system;
+
+ /** Request id for prefetches */
+ MasterID masterId;
+
public:
Stats::Scalar pfIdentified;
diff --git a/src/mem/cache/prefetch/ghb.cc b/src/mem/cache/prefetch/ghb.cc
index b9fc8e675..8e42a4e2b 100644
--- a/src/mem/cache/prefetch/ghb.cc
+++ b/src/mem/cache/prefetch/ghb.cc
@@ -42,20 +42,15 @@ void
GHBPrefetcher::calculatePrefetch(PacketPtr &pkt, std::list<Addr> &addresses,
std::list<Tick> &delays)
{
- if (useContextId && !pkt->req->hasContextId()) {
- DPRINTF(HWPrefetch, "ignoring request with no context ID");
- return;
- }
-
Addr blk_addr = pkt->getAddr() & ~(Addr)(blkSize-1);
- int ctx_id = useContextId ? pkt->req->contextId() : 0;
- assert(ctx_id < Max_Contexts);
+ int master_id = useMasterId ? pkt->req->masterId() : 0;
+ assert(master_id < Max_Masters);
- int new_stride = blk_addr - lastMissAddr[ctx_id];
- int old_stride = lastMissAddr[ctx_id] - secondLastMissAddr[ctx_id];
+ int new_stride = blk_addr - lastMissAddr[master_id];
+ int old_stride = lastMissAddr[master_id] - secondLastMissAddr[master_id];
- secondLastMissAddr[ctx_id] = lastMissAddr[ctx_id];
- lastMissAddr[ctx_id] = blk_addr;
+ secondLastMissAddr[master_id] = lastMissAddr[master_id];
+ lastMissAddr[master_id] = blk_addr;
if (new_stride == old_stride) {
for (int d = 1; d <= degree; d++) {
diff --git a/src/mem/cache/prefetch/ghb.hh b/src/mem/cache/prefetch/ghb.hh
index a21b57b93..ff713876a 100644
--- a/src/mem/cache/prefetch/ghb.hh
+++ b/src/mem/cache/prefetch/ghb.hh
@@ -43,10 +43,10 @@ class GHBPrefetcher : public BasePrefetcher
{
protected:
- static const int Max_Contexts = 64;
+ static const int Max_Masters = 64;
- Addr secondLastMissAddr[Max_Contexts];
- Addr lastMissAddr[Max_Contexts];
+ Addr secondLastMissAddr[Max_Masters];
+ Addr lastMissAddr[Max_Masters];
public:
GHBPrefetcher(const Params *p)
diff --git a/src/mem/cache/prefetch/stride.cc b/src/mem/cache/prefetch/stride.cc
index 645bc5fc5..feaa9494e 100644
--- a/src/mem/cache/prefetch/stride.cc
+++ b/src/mem/cache/prefetch/stride.cc
@@ -47,16 +47,11 @@ StridePrefetcher::calculatePrefetch(PacketPtr &pkt, std::list<Addr> &addresses,
return;
}
- if (useContextId && !pkt->req->hasContextId()) {
- DPRINTF(HWPrefetch, "ignoring request with no context ID");
- return;
- }
-
Addr blk_addr = pkt->getAddr() & ~(Addr)(blkSize-1);
- int ctx_id = useContextId ? pkt->req->contextId() : 0;
+ MasterID master_id = useMasterId ? pkt->req->masterId() : 0;
Addr pc = pkt->req->getPC();
- assert(ctx_id < Max_Contexts);
- std::list<StrideEntry*> &tab = table[ctx_id];
+ assert(master_id < Max_Contexts);
+ std::list<StrideEntry*> &tab = table[master_id];
/* Scan Table for instAddr Match */
std::list<StrideEntry*>::iterator iter;
diff --git a/src/mem/cache/tags/iic.cc b/src/mem/cache/tags/iic.cc
index acce3ffc8..3501ec378 100644
--- a/src/mem/cache/tags/iic.cc
+++ b/src/mem/cache/tags/iic.cc
@@ -369,7 +369,7 @@ IIC::freeReplacementBlock(PacketList & writebacks)
tag_ptr->size);
*/
Request *writebackReq = new Request(regenerateBlkAddr(tag_ptr->tag, 0),
- blkSize, 0);
+ blkSize, 0, Request::wbMasterId);
PacketPtr writeback = new Packet(writebackReq, MemCmd::Writeback,
-1);
writeback->allocate();
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-05 22:12:02 +0000