3 files changed, 7 insertions, 7 deletions
diff --git a/src/mem/cache/Cache.py b/src/mem/cache/Cache.py
index 0a590c2ca..b2f478472 100644
--- a/src/mem/cache/Cache.py
+++ b/src/mem/cache/Cache.py
@@ -43,7 +43,7 @@ from m5.params import *
 from m5.proxy import *
 from m5.SimObject import SimObject
 
-from m5.objects.MemObject import MemObject
+from m5.objects.ClockedObject import ClockedObject
 from m5.objects.Prefetcher import BasePrefetcher
 from m5.objects.ReplacementPolicies import *
 from m5.objects.Tags import *
@@ -72,7 +72,7 @@ class WriteAllocator(SimObject):
     block_size = Param.Int(Parent.cache_line_size, "block size in bytes")
 
 
-class BaseCache(MemObject):
+class BaseCache(ClockedObject):
     type = 'BaseCache'
     abstract = True
     cxx_header = "mem/cache/base.hh"
diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc
index 554a61eb0..f087618c7 100644
--- a/src/mem/cache/base.cc
+++ b/src/mem/cache/base.cc
@@ -77,7 +77,7 @@ BaseCache::CacheSlavePort::CacheSlavePort(const std::string &_name,
 }
 
 BaseCache::BaseCache(const BaseCacheParams *p, unsigned blk_size)
-    : MemObject(p),
+    : ClockedObject(p),
       cpuSidePort (p->name + ".cpu_side", this, "CpuSidePort"),
       memSidePort(p->name + ".mem_side", this, "MemSidePort"),
       mshrQueue("MSHRs", p->mshrs, 0, p->demand_mshr_reserve), // see below
@@ -193,7 +193,7 @@ BaseCache::getPort(const std::string &if_name, PortID idx)
     } else if (if_name == "cpu_side") {
         return cpuSidePort;
     }  else {
-        return MemObject::getPort(if_name, idx);
+        return ClockedObject::getPort(if_name, idx);
     }
 }
 
@@ -1696,7 +1696,7 @@ BaseCache::unserialize(CheckpointIn &cp)
 void
 BaseCache::regStats()
 {
-    MemObject::regStats();
+    ClockedObject::regStats();
 
     using namespace Stats;
 
diff --git a/src/mem/cache/base.hh b/src/mem/cache/base.hh
index 8d5ed11d0..b995a6e47 100644
--- a/src/mem/cache/base.hh
+++ b/src/mem/cache/base.hh
@@ -68,12 +68,12 @@
 #include "mem/cache/tags/base.hh"
 #include "mem/cache/write_queue.hh"
 #include "mem/cache/write_queue_entry.hh"
-#include "mem/mem_object.hh"
 #include "mem/packet.hh"
 #include "mem/packet_queue.hh"
 #include "mem/qport.hh"
 #include "mem/request.hh"
 #include "params/WriteAllocator.hh"
+#include "sim/clocked_object.hh"
 #include "sim/eventq.hh"
 #include "sim/probe/probe.hh"
 #include "sim/serialize.hh"
@@ -91,7 +91,7 @@ struct BaseCacheParams;
 /**
  * A basic cache interface. Implements some common functions for speed.
  */
-class BaseCache : public MemObject
+class BaseCache : public ClockedObject
 {
   protected:
     /**