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-rw-r--r--src/mem/cache/base_cache.cc68
-rw-r--r--src/mem/cache/base_cache.hh70
-rw-r--r--src/mem/cache/cache.hh17
-rw-r--r--src/mem/cache/cache_impl.hh2
-rw-r--r--src/mem/cache/miss/miss_queue.cc8
-rw-r--r--src/mem/cache/miss/mshr.cc1
6 files changed, 132 insertions, 34 deletions
diff --git a/src/mem/cache/base_cache.cc b/src/mem/cache/base_cache.cc
index aaaf1bdef..451da28e8 100644
--- a/src/mem/cache/base_cache.cc
+++ b/src/mem/cache/base_cache.cc
@@ -59,7 +59,7 @@ void
BaseCache::CachePort::getDeviceAddressRanges(AddrRangeList &resp,
AddrRangeList &snoop)
{
- cache->getAddressRanges(resp, snoop);
+ cache->getAddressRanges(resp, snoop, isCpuSide);
}
int
@@ -98,6 +98,56 @@ BaseCache::CachePort::clearBlocked()
blocked = false;
}
+BaseCache::CacheEvent::CacheEvent(CachePort *_cachePort)
+ : Event(&mainEventQueue, CPU_Tick_Pri), cachePort(_cachePort)
+{
+ this->setFlags(AutoDelete);
+ pkt = NULL;
+}
+
+BaseCache::CacheEvent::CacheEvent(CachePort *_cachePort, Packet *_pkt)
+ : Event(&mainEventQueue, CPU_Tick_Pri), cachePort(_cachePort), pkt(_pkt)
+{
+ this->setFlags(AutoDelete);
+}
+
+void
+BaseCache::CacheEvent::process()
+{
+ if (!pkt)
+ {
+ if (!cachePort->isCpuSide)
+ {
+ pkt = cachePort->cache->getPacket();
+ bool success = cachePort->sendTiming(pkt);
+ DPRINTF(Cache, "Address %x was %s in sending the timing request\n",
+ pkt->getAddr(), success ? "succesful" : "unsuccesful");
+ cachePort->cache->sendResult(pkt, success);
+ if (success && cachePort->cache->doMasterRequest())
+ {
+ //Still more to issue, rerequest in 1 cycle
+ pkt = NULL;
+ this->schedule(curTick+1);
+ }
+ }
+ else
+ {
+ pkt = cachePort->cache->getCoherencePacket();
+ cachePort->sendTiming(pkt);
+ }
+ return;
+ }
+ //Know the packet to send, no need to mark in service (must succed)
+ bool success = cachePort->sendTiming(pkt);
+ assert(success);
+}
+
+const char *
+BaseCache::CacheEvent::description()
+{
+ return "timing event\n";
+}
+
Port*
BaseCache::getPort(const std::string &if_name, int idx)
{
@@ -107,7 +157,13 @@ BaseCache::getPort(const std::string &if_name, int idx)
cpuSidePort = new CachePort(name() + "-cpu_side_port", this, true);
return cpuSidePort;
}
- if (if_name == "functional")
+ else if (if_name == "functional")
+ {
+ if(cpuSidePort == NULL)
+ cpuSidePort = new CachePort(name() + "-cpu_side_port", this, true);
+ return cpuSidePort;
+ }
+ else if (if_name == "cpu_side")
{
if(cpuSidePort == NULL)
cpuSidePort = new CachePort(name() + "-cpu_side_port", this, true);
@@ -124,6 +180,14 @@ BaseCache::getPort(const std::string &if_name, int idx)
}
void
+BaseCache::init()
+{
+ if (!cpuSidePort || !memSidePort)
+ panic("Cache not hooked up on both sides\n");
+ cpuSidePort->sendStatusChange(Port::RangeChange);
+}
+
+void
BaseCache::regStats()
{
Request temp_req((Addr) NULL, 4, 0);
diff --git a/src/mem/cache/base_cache.hh b/src/mem/cache/base_cache.hh
index 2754fab5a..0d1bfdfdb 100644
--- a/src/mem/cache/base_cache.hh
+++ b/src/mem/cache/base_cache.hh
@@ -79,9 +79,9 @@ class BaseCache : public MemObject
{
class CachePort : public Port
{
+ public:
BaseCache *cache;
- public:
CachePort(const std::string &_name, BaseCache *_cache, bool _isCpuSide);
protected:
@@ -110,10 +110,11 @@ class BaseCache : public MemObject
struct CacheEvent : public Event
{
- Packet *pkt;
CachePort *cachePort;
+ Packet *pkt;
- CacheEvent(Packet *pkt, CachePort *cachePort);
+ CacheEvent(CachePort *_cachePort);
+ CacheEvent(CachePort *_cachePort, Packet *_pkt);
void process();
const char *description();
};
@@ -142,11 +143,37 @@ class BaseCache : public MemObject
fatal("No implementation");
}
- virtual void recvStatusChange(Port::Status status, bool isCpuSide)
+ void recvStatusChange(Port::Status status, bool isCpuSide)
+ {
+ if (status == Port::RangeChange)
+ {
+ if (!isCpuSide)
+ {
+ cpuSidePort->sendStatusChange(Port::RangeChange);
+ }
+ else
+ {
+ memSidePort->sendStatusChange(Port::RangeChange);
+ }
+ }
+ }
+
+ virtual Packet *getPacket()
{
fatal("No implementation");
}
+ virtual Packet *getCoherencePacket()
+ {
+ fatal("No implementation");
+ }
+
+ virtual void sendResult(Packet* &pkt, bool success)
+ {
+
+ fatal("No implementation");
+ }
+
/**
* Bit vector of the blocking reasons for the access path.
* @sa #BlockedCause
@@ -303,6 +330,8 @@ class BaseCache : public MemObject
memSidePort = NULL;
}
+ virtual void init();
+
/**
* Query block size of a cache.
* @return The block size
@@ -388,7 +417,6 @@ class BaseCache : public MemObject
if (!isBlockedForSnoop()) {
memSidePort->clearBlocked();
}
-
}
/**
@@ -407,10 +435,13 @@ class BaseCache : public MemObject
*/
void setMasterRequest(RequestCause cause, Tick time)
{
+ if (!doMasterRequest())
+ {
+ BaseCache::CacheEvent * reqCpu = new BaseCache::CacheEvent(memSidePort);
+ reqCpu->schedule(time);
+ }
uint8_t flag = 1<<cause;
masterRequests |= flag;
- assert("Implement\n" && 0);
-// mi->pktuest(time);
}
/**
@@ -462,8 +493,10 @@ class BaseCache : public MemObject
*/
void respond(Packet *pkt, Tick time)
{
- assert("Implement\n" && 0);
-// si->respond(pkt,time);
+ pkt->makeTimingResponse();
+ pkt->result = Packet::Success;
+ CacheEvent *reqCpu = new CacheEvent(cpuSidePort, pkt);
+ reqCpu->schedule(time);
}
/**
@@ -476,8 +509,10 @@ class BaseCache : public MemObject
if (!pkt->req->isUncacheable()) {
missLatency[pkt->cmdToIndex()][pkt->req->getThreadNum()] += time - pkt->time;
}
- assert("Implement\n" && 0);
-// si->respond(pkt,time);
+ pkt->makeTimingResponse();
+ pkt->result = Packet::Success;
+ CacheEvent *reqCpu = new CacheEvent(cpuSidePort, pkt);
+ reqCpu->schedule(time);
}
/**
@@ -496,9 +531,18 @@ class BaseCache : public MemObject
*/
void rangeChange() {}
- void getAddressRanges(AddrRangeList &resp, AddrRangeList &snoop)
+ void getAddressRanges(AddrRangeList &resp, AddrRangeList &snoop, bool isCpuSide)
{
- panic("Unimplimented\n");
+ if (isCpuSide)
+ {
+ AddrRangeList dummy;
+ memSidePort->getPeerAddressRanges(resp, dummy);
+ }
+ else
+ {
+ //This is where snoops get updated
+ return;
+ }
}
};
diff --git a/src/mem/cache/cache.hh b/src/mem/cache/cache.hh
index 1243c9d9e..ec5b800a8 100644
--- a/src/mem/cache/cache.hh
+++ b/src/mem/cache/cache.hh
@@ -168,14 +168,14 @@ class Cache : public BaseCache
* Selects a request to send on the bus.
* @return The memory request to service.
*/
- Packet * getPacket();
+ virtual Packet * getPacket();
/**
* Was the request was sent successfully?
* @param req The request.
* @param success True if the request was sent successfully.
*/
- void sendResult(Packet * &pkt, bool success);
+ virtual void sendResult(Packet * &pkt, bool success);
/**
* Handles a response (cache line fill/write ack) from the bus.
@@ -202,7 +202,7 @@ class Cache : public BaseCache
* Selects a coherence message to forward to lower levels of the hierarchy.
* @return The coherence message to forward.
*/
- Packet * getCoherenceReq();
+ virtual Packet * getCoherencePacket();
/**
* Snoops bus transactions to maintain coherence.
@@ -242,17 +242,6 @@ class Cache : public BaseCache
}
/**
- * Send a response to the slave interface.
- * @param req The request being responded to.
- * @param time The time the response is ready.
- */
- void respond(Packet * &pkt, Tick time)
- {
- //si->respond(pkt,time);
- cpuSidePort->sendAtomic(pkt);
- }
-
- /**
* Perform the access specified in the request and return the estimated
* time of completion. This function can either update the hierarchy state
* or just perform the access wherever the data is found depending on the
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index aae5cbf01..a447ae3d5 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -350,7 +350,7 @@ Cache<TagStore,Buffering,Coherence>::pseudoFill(MSHR *mshr)
template<class TagStore, class Buffering, class Coherence>
Packet *
-Cache<TagStore,Buffering,Coherence>::getCoherenceReq()
+Cache<TagStore,Buffering,Coherence>::getCoherencePacket()
{
return coherence->getPacket();
}
diff --git a/src/mem/cache/miss/miss_queue.cc b/src/mem/cache/miss/miss_queue.cc
index da0448ad3..4a3dc1062 100644
--- a/src/mem/cache/miss/miss_queue.cc
+++ b/src/mem/cache/miss/miss_queue.cc
@@ -352,7 +352,7 @@ MissQueue::setPrefetcher(BasePrefetcher *_prefetcher)
MSHR*
MissQueue::allocateMiss(Packet * &pkt, int size, Tick time)
{
- MSHR* mshr = mq.allocate(pkt, size);
+ MSHR* mshr = mq.allocate(pkt, blkSize);
mshr->order = order++;
if (!pkt->req->isUncacheable() ){//&& !pkt->isNoAllocate()) {
// Mark this as a cache line fill
@@ -372,7 +372,7 @@ MissQueue::allocateMiss(Packet * &pkt, int size, Tick time)
MSHR*
MissQueue::allocateWrite(Packet * &pkt, int size, Tick time)
{
- MSHR* mshr = wb.allocate(pkt,pkt->getSize());
+ MSHR* mshr = wb.allocate(pkt,blkSize);
mshr->order = order++;
//REMOVING COMPRESSION FOR NOW
@@ -446,11 +446,11 @@ MissQueue::handleMiss(Packet * &pkt, int blkSize, Tick time)
/**
* @todo Add write merging here.
*/
- mshr = allocateWrite(pkt, pkt->getSize(), time);
+ mshr = allocateWrite(pkt, blkSize, time);
return;
}
- mshr = allocateMiss(pkt, size, time);
+ mshr = allocateMiss(pkt, blkSize, time);
}
MSHR*
diff --git a/src/mem/cache/miss/mshr.cc b/src/mem/cache/miss/mshr.cc
index 1a85d3018..db2f40c56 100644
--- a/src/mem/cache/miss/mshr.cc
+++ b/src/mem/cache/miss/mshr.cc
@@ -57,6 +57,7 @@ void
MSHR::allocate(Packet::Command cmd, Addr _addr, int _asid, int size,
Packet * &target)
{
+ addr = _addr;
if (target)
{
//Have a request, just use it
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-01 00:28:17 +0000