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-rw-r--r--src/mem/cache/blk.hh4
-rw-r--r--src/mem/cache/cache_impl.hh4
2 files changed, 4 insertions, 4 deletions
diff --git a/src/mem/cache/blk.hh b/src/mem/cache/blk.hh
index fe65672d6..acb117f6c 100644
--- a/src/mem/cache/blk.hh
+++ b/src/mem/cache/blk.hh
@@ -218,7 +218,7 @@ class CacheBlk
*/
void trackLoadLocked(PacketPtr pkt)
{
- assert(pkt->isLocked());
+ assert(pkt->isLlsc());
lockList.push_front(Lock(pkt->req));
}
@@ -236,7 +236,7 @@ class CacheBlk
bool checkWrite(PacketPtr pkt)
{
Request *req = pkt->req;
- if (pkt->isLocked()) {
+ if (pkt->isLlsc()) {
// it's a store conditional... have to check for matching
// load locked.
bool success = false;
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index a78fd3637..f98d6ac34 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -180,7 +180,7 @@ Cache<TagStore>::satisfyCpuSideRequest(PacketPtr pkt, BlkType *blk)
pkt->writeDataToBlock(blk->data, blkSize);
}
} else if (pkt->isRead()) {
- if (pkt->isLocked()) {
+ if (pkt->isLlsc()) {
blk->trackLoadLocked(pkt);
}
pkt->setDataFromBlock(blk->data, blkSize);
@@ -317,7 +317,7 @@ Cache<TagStore>::access(PacketPtr pkt, BlkType *&blk,
incMissCount(pkt);
- if (blk == NULL && pkt->isLocked() && pkt->isWrite()) {
+ if (blk == NULL && pkt->isLlsc() && pkt->isWrite()) {
// complete miss on store conditional... just give up now
pkt->req->setExtraData(0);
return true;