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-rw-r--r--src/mem/cache/blk.hh20
-rw-r--r--src/mem/cache/builder.cc74
-rw-r--r--src/mem/cache/prefetch/stride.cc4
-rw-r--r--src/mem/cache/prefetch/stride.hh2
-rw-r--r--src/mem/cache/tags/iic.cc2
-rw-r--r--src/mem/cache/tags/lru.cc4
-rw-r--r--src/mem/cache/tags/lru.hh2
-rw-r--r--src/mem/cache/tags/split_lru.cc4
8 files changed, 56 insertions, 56 deletions
diff --git a/src/mem/cache/blk.hh b/src/mem/cache/blk.hh
index 127c547ac..9bfbd646d 100644
--- a/src/mem/cache/blk.hh
+++ b/src/mem/cache/blk.hh
@@ -38,8 +38,8 @@
#include <list>
#include "base/printable.hh"
-#include "sim/core.hh" // for Tick
-#include "arch/isa_traits.hh" // for Addr
+#include "sim/core.hh" // for Tick
+#include "arch/isa_traits.hh" // for Addr
#include "mem/packet.hh"
#include "mem/request.hh"
@@ -48,17 +48,17 @@
*/
enum CacheBlkStatusBits {
/** valid, readable */
- BlkValid = 0x01,
+ BlkValid = 0x01,
/** write permission */
- BlkWritable = 0x02,
+ BlkWritable = 0x02,
/** read permission (yes, block can be valid but not readable) */
- BlkReadable = 0x04,
+ BlkReadable = 0x04,
/** dirty (modified) */
- BlkDirty = 0x08,
+ BlkDirty = 0x08,
/** block was referenced */
- BlkReferenced = 0x10,
+ BlkReferenced = 0x10,
/** block was a hardware prefetch yet unaccessed*/
- BlkHWPrefetched = 0x20
+ BlkHWPrefetched = 0x20
};
/**
@@ -108,8 +108,8 @@ class CacheBlk
*/
class Lock {
public:
- int cpuNum; // locking CPU
- int threadNum; // locking thread ID within CPU
+ int cpuNum; // locking CPU
+ int threadNum; // locking thread ID within CPU
// check for matching execution context
bool matchesContext(Request *req)
diff --git a/src/mem/cache/builder.cc b/src/mem/cache/builder.cc
index db900c64c..97930fe60 100644
--- a/src/mem/cache/builder.cc
+++ b/src/mem/cache/builder.cc
@@ -100,101 +100,101 @@ using namespace TheISA;
return retval; \
} while (0)
-#define BUILD_CACHE_PANIC(x) do { \
- panic("%s not compiled into M5", x); \
+#define BUILD_CACHE_PANIC(x) do { \
+ panic("%s not compiled into M5", x); \
} while (0)
#if defined(USE_CACHE_FALRU)
-#define BUILD_FALRU_CACHE do { \
+#define BUILD_FALRU_CACHE do { \
FALRU *tags = new FALRU(block_size, size, latency); \
- BUILD_CACHE(FALRU, tags); \
+ BUILD_CACHE(FALRU, tags); \
} while (0)
#else
#define BUILD_FALRU_CACHE BUILD_CACHE_PANIC("falru cache")
#endif
#if defined(USE_CACHE_LRU)
-#define BUILD_LRU_CACHE do { \
- LRU *tags = new LRU(numSets, block_size, assoc, latency); \
- BUILD_CACHE(LRU, tags); \
+#define BUILD_LRU_CACHE do { \
+ LRU *tags = new LRU(numSets, block_size, assoc, latency); \
+ BUILD_CACHE(LRU, tags); \
} while (0)
#else
#define BUILD_LRU_CACHE BUILD_CACHE_PANIC("lru cache")
#endif
#if defined(USE_CACHE_SPLIT)
-#define BUILD_SPLIT_CACHE do { \
+#define BUILD_SPLIT_CACHE do { \
Split *tags = new Split(numSets, block_size, assoc, split_size, lifo, \
- two_queue, latency); \
- BUILD_CACHE(Split, tags); \
+ two_queue, latency); \
+ BUILD_CACHE(Split, tags); \
} while (0)
#else
#define BUILD_SPLIT_CACHE BUILD_CACHE_PANIC("split cache")
#endif
#if defined(USE_CACHE_SPLIT_LIFO)
-#define BUILD_SPLIT_LIFO_CACHE do { \
+#define BUILD_SPLIT_LIFO_CACHE do { \
SplitLIFO *tags = new SplitLIFO(block_size, size, assoc, \
- latency, two_queue, -1); \
- BUILD_CACHE(SplitLIFO, tags); \
+ latency, two_queue, -1); \
+ BUILD_CACHE(SplitLIFO, tags); \
} while (0)
#else
#define BUILD_SPLIT_LIFO_CACHE BUILD_CACHE_PANIC("lifo cache")
#endif
#if defined(USE_CACHE_IIC)
-#define BUILD_IIC_CACHE do { \
- IIC *tags = new IIC(iic_params); \
- BUILD_CACHE(IIC, tags); \
+#define BUILD_IIC_CACHE do { \
+ IIC *tags = new IIC(iic_params); \
+ BUILD_CACHE(IIC, tags); \
} while (0)
#else
#define BUILD_IIC_CACHE BUILD_CACHE_PANIC("iic")
#endif
-#define BUILD_CACHES do { \
- if (repl == NULL) { \
- if (numSets == 1) { \
- BUILD_FALRU_CACHE; \
- } else { \
- if (split == true) { \
- BUILD_SPLIT_CACHE; \
- } else if (lifo == true) { \
- BUILD_SPLIT_LIFO_CACHE; \
- } else { \
- BUILD_LRU_CACHE; \
- } \
- } \
- } else { \
- BUILD_IIC_CACHE; \
- } \
+#define BUILD_CACHES do { \
+ if (repl == NULL) { \
+ if (numSets == 1) { \
+ BUILD_FALRU_CACHE; \
+ } else { \
+ if (split == true) { \
+ BUILD_SPLIT_CACHE; \
+ } else if (lifo == true) { \
+ BUILD_SPLIT_LIFO_CACHE; \
+ } else { \
+ BUILD_LRU_CACHE; \
+ } \
+ } \
+ } else { \
+ BUILD_IIC_CACHE; \
+ } \
} while (0)
-#define BUILD_COHERENCE(b) do { \
+#define BUILD_COHERENCE(b) do { \
} while (0)
#if defined(USE_TAGGED)
-#define BUILD_TAGGED_PREFETCHER(t) \
+#define BUILD_TAGGED_PREFETCHER(t) \
pf = new TaggedPrefetcher(this)
#else
#define BUILD_TAGGED_PREFETCHER(t) BUILD_CACHE_PANIC("Tagged Prefetcher")
#endif
#if defined(USE_STRIDED)
-#define BUILD_STRIDED_PREFETCHER(t) \
+#define BUILD_STRIDED_PREFETCHER(t) \
pf = new StridePrefetcher(this)
#else
#define BUILD_STRIDED_PREFETCHER(t) BUILD_CACHE_PANIC("Stride Prefetcher")
#endif
#if defined(USE_GHB)
-#define BUILD_GHB_PREFETCHER(t) \
+#define BUILD_GHB_PREFETCHER(t) \
pf = new GHBPrefetcher(this)
#else
#define BUILD_GHB_PREFETCHER(t) BUILD_CACHE_PANIC("GHB Prefetcher")
#endif
#if defined(USE_TAGGED)
-#define BUILD_NULL_PREFETCHER(t) \
+#define BUILD_NULL_PREFETCHER(t) \
pf = new TaggedPrefetcher(this)
#else
#define BUILD_NULL_PREFETCHER(t) BUILD_CACHE_PANIC("NULL Prefetcher (uses Tagged)")
diff --git a/src/mem/cache/prefetch/stride.cc b/src/mem/cache/prefetch/stride.cc
index b116b66c7..e93058d6e 100644
--- a/src/mem/cache/prefetch/stride.cc
+++ b/src/mem/cache/prefetch/stride.cc
@@ -40,12 +40,12 @@ void
StridePrefetcher::calculatePrefetch(PacketPtr &pkt, std::list<Addr> &addresses,
std::list<Tick> &delays)
{
-// Addr blkAddr = pkt->paddr & ~(Addr)(this->blkSize-1);
+// Addr blkAddr = pkt->paddr & ~(Addr)(this->blkSize-1);
int cpuID = pkt->req->getCpuNum();
if (!useCPUId) cpuID = 0;
/* Scan Table for IAddr Match */
-/* std::list<strideEntry*>::iterator iter;
+/* std::list<strideEntry*>::iterator iter;
for (iter=table[cpuID].begin();
iter !=table[cpuID].end();
iter++) {
diff --git a/src/mem/cache/prefetch/stride.hh b/src/mem/cache/prefetch/stride.hh
index f6bdbc424..ca173277c 100644
--- a/src/mem/cache/prefetch/stride.hh
+++ b/src/mem/cache/prefetch/stride.hh
@@ -50,7 +50,7 @@ class StridePrefetcher : public BasePrefetcher
int stride;
int64_t confidence;
-/* bool operator < (strideEntry a,strideEntry b)
+/* bool operator < (strideEntry a,strideEntry b)
{
if (a.confidence == b.confidence) {
return true; //??????
diff --git a/src/mem/cache/tags/iic.cc b/src/mem/cache/tags/iic.cc
index 2825599f6..af9a75d43 100644
--- a/src/mem/cache/tags/iic.cc
+++ b/src/mem/cache/tags/iic.cc
@@ -365,7 +365,7 @@ IIC::freeReplacementBlock(PacketList & writebacks)
tag_ptr->refCount = 0;
if (tag_ptr->isDirty()) {
-/* PacketPtr writeback =
+/* PacketPtr writeback =
buildWritebackReq(regenerateBlkAddr(tag_ptr->tag, 0),
tag_ptr->req->asid, tag_ptr->xc, blkSize,
tag_ptr->data,
diff --git a/src/mem/cache/tags/lru.cc b/src/mem/cache/tags/lru.cc
index 7f352e9c4..7fb5318a0 100644
--- a/src/mem/cache/tags/lru.cc
+++ b/src/mem/cache/tags/lru.cc
@@ -113,7 +113,7 @@ LRU::LRU(int _numSets, int _blkSize, int _assoc, int _hit_latency) :
// allocate data storage in one big chunk
dataBlks = new uint8_t[numSets*assoc*blkSize];
- blkIndex = 0; // index into blks array
+ blkIndex = 0; // index into blks array
for (i = 0; i < numSets; ++i) {
sets[i].assoc = assoc;
@@ -160,7 +160,7 @@ LRU::probe(Addr addr) const
LRUBlk *blk = sets[myset].findBlk(tag);
- return (blk != NULL); // true if in cache
+ return (blk != NULL); // true if in cache
}
LRUBlk*
diff --git a/src/mem/cache/tags/lru.hh b/src/mem/cache/tags/lru.hh
index ea5606cde..65be492de 100644
--- a/src/mem/cache/tags/lru.hh
+++ b/src/mem/cache/tags/lru.hh
@@ -127,7 +127,7 @@ public:
* @param _assoc The associativity of the cache.
* @param _hit_latency The latency in cycles for a hit.
*/
- LRU(int _numSets, int _blkSize, int _assoc, int _hit_latency);
+ LRU(int _numSets, int _blkSize, int _assoc, int _hit_latency);
/**
* Destructor
diff --git a/src/mem/cache/tags/split_lru.cc b/src/mem/cache/tags/split_lru.cc
index bcccdcb30..2b01b07cd 100644
--- a/src/mem/cache/tags/split_lru.cc
+++ b/src/mem/cache/tags/split_lru.cc
@@ -113,7 +113,7 @@ SplitLRU::SplitLRU(int _numSets, int _blkSize, int _assoc, int _hit_latency, int
// allocate data storage in one big chunk
dataBlks = new uint8_t[numSets*assoc*blkSize];
- blkIndex = 0; // index into blks array
+ blkIndex = 0; // index into blks array
for (i = 0; i < numSets; ++i) {
sets[i].assoc = assoc;
@@ -179,7 +179,7 @@ SplitLRU::probe(Addr addr) const
SplitBlk *blk = sets[myset].findBlk(tag);
- return (blk != NULL); // true if in cache
+ return (blk != NULL); // true if in cache
}
SplitBlk*
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-30 16:31:00 +0000