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-rw-r--r--src/mem/cache/base_cache.cc68
-rw-r--r--src/mem/cache/base_cache.hh27
-rw-r--r--src/mem/cache/cache_blk.hh19
-rw-r--r--src/mem/cache/cache_impl.hh14
-rw-r--r--src/mem/cache/coherence/uni_coherence.cc14
-rw-r--r--src/mem/cache/miss/miss_queue.cc2
6 files changed, 72 insertions, 72 deletions
diff --git a/src/mem/cache/base_cache.cc b/src/mem/cache/base_cache.cc
index 71ea58416..3f7a52fab 100644
--- a/src/mem/cache/base_cache.cc
+++ b/src/mem/cache/base_cache.cc
@@ -107,6 +107,42 @@ BaseCache::CachePort::recvAtomic(Packet *pkt)
void
BaseCache::CachePort::recvFunctional(Packet *pkt)
{
+ //Check storage here first
+ list<Packet *>::iterator i = drainList.begin();
+ list<Packet *>::iterator end = drainList.end();
+ for (; i != end; ++i) {
+ Packet * target = *i;
+ // If the target contains data, and it overlaps the
+ // probed request, need to update data
+ if (target->intersect(pkt)) {
+ uint8_t* pkt_data;
+ uint8_t* write_data;
+ int data_size;
+ if (target->getAddr() < pkt->getAddr()) {
+ int offset = pkt->getAddr() - target->getAddr();
+ pkt_data = pkt->getPtr<uint8_t>();
+ write_data = target->getPtr<uint8_t>() + offset;
+ data_size = target->getSize() - offset;
+ assert(data_size > 0);
+ if (data_size > pkt->getSize())
+ data_size = pkt->getSize();
+ } else {
+ int offset = target->getAddr() - pkt->getAddr();
+ pkt_data = pkt->getPtr<uint8_t>() + offset;
+ write_data = target->getPtr<uint8_t>();
+ data_size = pkt->getSize() - offset;
+ assert(data_size > pkt->getSize());
+ if (data_size > target->getSize())
+ data_size = target->getSize();
+ }
+
+ if (pkt->isWrite()) {
+ memcpy(pkt_data, write_data, data_size);
+ } else {
+ memcpy(write_data, pkt_data, data_size);
+ }
+ }
+ }
cache->doFunctionalAccess(pkt, isCpuSide);
}
@@ -153,7 +189,6 @@ BaseCache::CachePort::recvRetry()
{
DPRINTF(CachePort, "%s has more requests\n", name());
//Still more to issue, rerequest in 1 cycle
- pkt = NULL;
BaseCache::CacheEvent * reqCpu = new BaseCache::CacheEvent(this);
reqCpu->schedule(curTick + 1);
}
@@ -166,12 +201,13 @@ BaseCache::CachePort::recvRetry()
pkt = cshrRetry;
bool success = sendTiming(pkt);
waitingOnRetry = !success;
- if (success && cache->doSlaveRequest())
+ if (success)
{
- //Still more to issue, rerequest in 1 cycle
- pkt = NULL;
- BaseCache::CacheEvent * reqCpu = new BaseCache::CacheEvent(this);
- reqCpu->schedule(curTick + 1);
+ if (cache->doSlaveRequest()) {
+ //Still more to issue, rerequest in 1 cycle
+ BaseCache::CacheEvent * reqCpu = new BaseCache::CacheEvent(this);
+ reqCpu->schedule(curTick + 1);
+ }
cshrRetry = NULL;
}
}
@@ -269,20 +305,28 @@ BaseCache::CacheEvent::process()
}
else
{
- assert(cachePort->cache->doSlaveRequest());
//CSHR
- pkt = cachePort->cache->getCoherencePacket();
+ if (!cachePort->cshrRetry) {
+ assert(cachePort->cache->doSlaveRequest());
+ pkt = cachePort->cache->getCoherencePacket();
+ }
+ else {
+ pkt = cachePort->cshrRetry;
+ }
bool success = cachePort->sendTiming(pkt);
if (!success) {
//Need to send on a retry
cachePort->cshrRetry = pkt;
cachePort->waitingOnRetry = true;
}
- else if (cachePort->cache->doSlaveRequest())
+ else
{
- //Still more to issue, rerequest in 1 cycle
- pkt = NULL;
- this->schedule(curTick+1);
+ cachePort->cshrRetry = NULL;
+ if (cachePort->cache->doSlaveRequest()) {
+ //Still more to issue, rerequest in 1 cycle
+ pkt = NULL;
+ this->schedule(curTick+1);
+ }
}
}
return;
diff --git a/src/mem/cache/base_cache.hh b/src/mem/cache/base_cache.hh
index 563b1ca8b..455e13d9c 100644
--- a/src/mem/cache/base_cache.hh
+++ b/src/mem/cache/base_cache.hh
@@ -212,10 +212,6 @@ class BaseCache : public MemObject
protected:
- /** True if this cache is connected to the CPU. */
- bool topLevelCache;
-
-
/** Stores time the cache blocked for statistics. */
Tick blockedCycle;
@@ -337,7 +333,7 @@ class BaseCache : public MemObject
*/
BaseCache(const std::string &name, Params &params)
: MemObject(name), blocked(0), blockedSnoop(0), masterRequests(0),
- slaveRequests(0), topLevelCache(false), blkSize(params.blkSize),
+ slaveRequests(0), blkSize(params.blkSize),
missCount(params.maxMisses)
{
//Start ports at null if more than one is created we should panic
@@ -358,15 +354,6 @@ class BaseCache : public MemObject
}
/**
- * Returns true if this cache is connect to the CPU.
- * @return True if this is a L1 cache.
- */
- bool isTopLevel()
- {
- return topLevelCache;
- }
-
- /**
* Returns true if the cache is blocked for accesses.
*/
bool isBlocked()
@@ -561,8 +548,6 @@ class BaseCache : public MemObject
*/
void respondToSnoop(Packet *pkt, Tick time)
{
-// assert("Implement\n" && 0);
-// mi->respond(pkt,curTick + hitLatency);
assert (pkt->needsResponse());
CacheEvent *reqMem = new CacheEvent(memSidePort, pkt);
reqMem->schedule(time);
@@ -585,15 +570,7 @@ class BaseCache : public MemObject
{
//This is where snoops get updated
AddrRangeList dummy;
-// if (!topLevelCache)
-// {
- cpuSidePort->getPeerAddressRanges(dummy, snoop);
-// }
-// else
-// {
-// snoop.push_back(RangeSize(0,-1));
-// }
-
+ cpuSidePort->getPeerAddressRanges(dummy, snoop);
return;
}
}
diff --git a/src/mem/cache/cache_blk.hh b/src/mem/cache/cache_blk.hh
index a75c9611d..078c82d82 100644
--- a/src/mem/cache/cache_blk.hh
+++ b/src/mem/cache/cache_blk.hh
@@ -38,8 +38,6 @@
#include "sim/root.hh" // for Tick
#include "arch/isa_traits.hh" // for Addr
-#include <iostream>
-
/**
* Cache block status bit assignments
*/
@@ -180,21 +178,4 @@ class CacheBlk
};
-/**
- * Output a CacheBlk to the given ostream.
- * @param out The stream for the output.
- * @param blk The cache block to print.
- *
- * @return The output stream.
- */
-inline std::ostream &
-operator<<(std::ostream &out, const CacheBlk &blk)
-{
- out << std::hex << std::endl;
- out << " Tag: " << blk.tag << std::endl;
- out << " Status: " << blk.status << std::endl;
-
- return(out << std::dec);
-}
-
#endif //__CACHE_BLK_HH__
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index a68418f24..9db79b843 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -151,12 +151,7 @@ Cache(const std::string &_name,
doCopy(params.doCopy), blockOnCopy(params.blockOnCopy),
hitLatency(params.hitLatency)
{
-//FIX BUS POINTERS
-// if (params.in == NULL) {
- topLevelCache = true;
-// }
-//PLEASE FIX THIS, BUS SIZES NOT BEING USED
- tags->setCache(this, blkSize, 1/*params.out->width, params.out->clockRate*/);
+ tags->setCache(this);
tags->setPrefetcher(prefetcher);
missQueue->setCache(this);
missQueue->setPrefetcher(prefetcher);
@@ -389,10 +384,15 @@ template<class TagStore, class Buffering, class Coherence>
void
Cache<TagStore,Buffering,Coherence>::snoop(Packet * &pkt)
{
+ if (pkt->req->isUncacheable()) {
+ //Can't get a hit on an uncacheable address
+ //Revisit this for multi level coherence
+ return;
+ }
Addr blk_addr = pkt->getAddr() & ~(Addr(blkSize-1));
BlkType *blk = tags->findBlock(pkt);
MSHR *mshr = missQueue->findMSHR(blk_addr);
- if (isTopLevel() && coherence->hasProtocol()) { //@todo Move this into handle bus req
+ if (coherence->hasProtocol()) { //@todo Move this into handle bus req
//If we find an mshr, and it is in service, we need to NACK or invalidate
if (mshr) {
if (mshr->inService) {
diff --git a/src/mem/cache/coherence/uni_coherence.cc b/src/mem/cache/coherence/uni_coherence.cc
index 5ab706269..0efe393f9 100644
--- a/src/mem/cache/coherence/uni_coherence.cc
+++ b/src/mem/cache/coherence/uni_coherence.cc
@@ -68,14 +68,12 @@ UniCoherence::handleBusRequest(Packet * &pkt, CacheBlk *blk, MSHR *mshr,
if (pkt->isInvalidate()) {
DPRINTF(Cache, "snoop inval on blk %x (blk ptr %x)\n",
pkt->getAddr(), blk);
- if (!cache->isTopLevel()) {
- // Forward to other caches
- Packet * tmp = new Packet(pkt->req, Packet::InvalidateReq, -1);
- cshrs.allocate(tmp);
- cache->setSlaveRequest(Request_Coherence, curTick);
- if (cshrs.isFull()) {
- cache->setBlockedForSnoop(Blocked_Coherence);
- }
+ // Forward to other caches
+ Packet * tmp = new Packet(pkt->req, Packet::InvalidateReq, -1);
+ cshrs.allocate(tmp);
+ cache->setSlaveRequest(Request_Coherence, curTick);
+ if (cshrs.isFull()) {
+ cache->setBlockedForSnoop(Blocked_Coherence);
}
} else {
if (blk) {
diff --git a/src/mem/cache/miss/miss_queue.cc b/src/mem/cache/miss/miss_queue.cc
index c7b0e0890..c23b542f5 100644
--- a/src/mem/cache/miss/miss_queue.cc
+++ b/src/mem/cache/miss/miss_queue.cc
@@ -352,7 +352,7 @@ MissQueue::setPrefetcher(BasePrefetcher *_prefetcher)
MSHR*
MissQueue::allocateMiss(Packet * &pkt, int size, Tick time)
{
- MSHR* mshr = mq.allocate(pkt, blkSize);
+ MSHR* mshr = mq.allocate(pkt, size);
mshr->order = order++;
if (!pkt->req->isUncacheable() ){//&& !pkt->isNoAllocate()) {
// Mark this as a cache line fill
generated by cgit v1.2.3 (git 2.25.1) at 2025-03-28 21:03:27 +0000