diff options
Diffstat (limited to 'src/mem/cache')
| -rw-r--r-- | src/mem/cache/BaseCache.py | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mem/cache/BaseCache.py b/src/mem/cache/BaseCache.py index 4389eb356..adc48a461 100644 --- a/src/mem/cache/BaseCache.py +++ b/src/mem/cache/BaseCache.py @@ -58,7 +58,7 @@ class BaseCache(MemObject): prefetch_on_access = Param.Bool(False, "notify the hardware prefetcher on every access (not just misses)") prefetcher = Param.BasePrefetcher(NULL,"Prefetcher attached to cache") - cpu_side = Port("Port on side closer to CPU") - mem_side = Port("Port on side closer to MEM") + cpu_side = SlavePort("Port on side closer to CPU") + mem_side = MasterPort("Port on side closer to MEM") addr_range = Param.AddrRange(AllMemory, "The address range for the CPU-side port") system = Param.System(Parent.any, "System we belong to") |