diff options
Diffstat (limited to 'src/mem/cache')
-rw-r--r-- | src/mem/cache/base_cache.cc | 14 | ||||
-rw-r--r-- | src/mem/cache/base_cache.hh | 7 | ||||
-rw-r--r-- | src/mem/cache/miss/miss_queue.cc | 2 |
3 files changed, 12 insertions, 11 deletions
diff --git a/src/mem/cache/base_cache.cc b/src/mem/cache/base_cache.cc index c16cb6945..3af61375d 100644 --- a/src/mem/cache/base_cache.cc +++ b/src/mem/cache/base_cache.cc @@ -160,11 +160,14 @@ BaseCache::CachePort::recvRetry() PacketPtr pkt; assert(waitingOnRetry); if (!drainList.empty()) { - DPRINTF(CachePort, "%s attempting to send a retry for response\n", name()); + DPRINTF(CachePort, "%s attempting to send a retry for response (%i waiting)\n" + , name(), drainList.size()); //We have some responses to drain first - if (sendTiming(drainList.front())) { - DPRINTF(CachePort, "%s sucessful in sending a retry for response\n", name()); - drainList.pop_front(); + pkt = drainList.front(); + drainList.pop_front(); + if (sendTiming(pkt)) { + DPRINTF(CachePort, "%s sucessful in sending a retry for" + "response (%i still waiting)\n", name(), drainList.size()); if (!drainList.empty() || !isCpuSide && cache->doMasterRequest() || isCpuSide && cache->doSlaveRequest()) { @@ -175,6 +178,9 @@ BaseCache::CachePort::recvRetry() } waitingOnRetry = false; } + else { + drainList.push_front(pkt); + } // Check if we're done draining once this list is empty if (drainList.empty()) cache->checkDrain(); diff --git a/src/mem/cache/base_cache.hh b/src/mem/cache/base_cache.hh index 584c2d5df..ef4955432 100644 --- a/src/mem/cache/base_cache.hh +++ b/src/mem/cache/base_cache.hh @@ -144,8 +144,6 @@ class BaseCache : public MemObject protected: CachePort *memSidePort; - bool snoopRangesSent; - public: virtual Port *getPort(const std::string &if_name, int idx = -1); @@ -171,10 +169,6 @@ class BaseCache : public MemObject if (status == Port::RangeChange){ if (!isCpuSide) { cpuSidePort->sendStatusChange(Port::RangeChange); - if (!snoopRangesSent) { - snoopRangesSent = true; - memSidePort->sendStatusChange(Port::RangeChange); - } } else { memSidePort->sendStatusChange(Port::RangeChange); @@ -358,7 +352,6 @@ class BaseCache : public MemObject //Start ports at null if more than one is created we should panic cpuSidePort = NULL; memSidePort = NULL; - snoopRangesSent = false; } ~BaseCache() diff --git a/src/mem/cache/miss/miss_queue.cc b/src/mem/cache/miss/miss_queue.cc index fe467a8ea..3c4586272 100644 --- a/src/mem/cache/miss/miss_queue.cc +++ b/src/mem/cache/miss/miss_queue.cc @@ -612,6 +612,8 @@ MissQueue::handleResponse(PacketPtr &pkt, Tick time) if (mshr->hasTargets()) { // Didn't satisfy all the targets, need to resend Packet::Command cmd = mshr->getTarget()->cmd; + mshr->pkt->setDest(Packet::Broadcast); + mshr->pkt->result = Packet::Unknown; mq.markPending(mshr, cmd); mshr->order = order++; cache->setMasterRequest(Request_MSHR, time); |